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authorDario Nieuwenhuis <[email protected]>2022-06-12 22:15:44 +0200
committerDario Nieuwenhuis <[email protected]>2022-06-12 22:22:31 +0200
commita8703b75988e1e700af701116464025679d2feb8 (patch)
treef4ec5de70ec05e793a774049e010935ac45853ed /embassy-lora/src
parent6199bdea710cde33e5d5381b6d6abfc8af46df19 (diff)
Run rustfmt.
Diffstat (limited to 'embassy-lora/src')
-rw-r--r--embassy-lora/src/stm32wl/mod.rs67
-rw-r--r--embassy-lora/src/sx127x/mod.rs7
-rw-r--r--embassy-lora/src/sx127x/sx127x_lora/mod.rs174
3 files changed, 69 insertions, 179 deletions
diff --git a/embassy-lora/src/stm32wl/mod.rs b/embassy-lora/src/stm32wl/mod.rs
index b5ce278dc..5f3dc17a7 100644
--- a/embassy-lora/src/stm32wl/mod.rs
+++ b/embassy-lora/src/stm32wl/mod.rs
@@ -1,25 +1,20 @@
1//! A radio driver integration for the radio found on STM32WL family devices. 1//! A radio driver integration for the radio found on STM32WL family devices.
2use core::future::Future; 2use core::future::Future;
3use core::mem::MaybeUninit; 3use core::mem::MaybeUninit;
4
4use embassy::channel::signal::Signal; 5use embassy::channel::signal::Signal;
5use embassy_hal_common::unborrow; 6use embassy_hal_common::unborrow;
6use embassy_stm32::interrupt::InterruptExt; 7use embassy_stm32::dma::NoDma;
7use embassy_stm32::Unborrow; 8use embassy_stm32::gpio::{AnyPin, Output};
8use embassy_stm32::{ 9use embassy_stm32::interrupt::{InterruptExt, SUBGHZ_RADIO};
9 dma::NoDma, 10use embassy_stm32::subghz::{
10 gpio::{AnyPin, Output}, 11 CalibrateImage, CfgIrq, CodingRate, HeaderType, Irq, LoRaBandwidth, LoRaModParams, LoRaPacketParams, LoRaSyncWord,
11 interrupt::SUBGHZ_RADIO, 12 Ocp, PaConfig, PaSel, PacketType, RampTime, RegMode, RfFreq, SpreadingFactor as SF, StandbyClk, Status, SubGhz,
12 subghz::{ 13 TcxoMode, TcxoTrim, Timeout, TxParams,
13 CalibrateImage, CfgIrq, CodingRate, HeaderType, Irq, LoRaBandwidth, LoRaModParams,
14 LoRaPacketParams, LoRaSyncWord, Ocp, PaConfig, PaSel, PacketType, RampTime, RegMode,
15 RfFreq, SpreadingFactor as SF, StandbyClk, Status, SubGhz, TcxoMode, TcxoTrim, Timeout,
16 TxParams,
17 },
18};
19use lorawan_device::async_device::{
20 radio::{Bandwidth, PhyRxTx, RfConfig, RxQuality, SpreadingFactor, TxConfig},
21 Timings,
22}; 14};
15use embassy_stm32::Unborrow;
16use lorawan_device::async_device::radio::{Bandwidth, PhyRxTx, RfConfig, RxQuality, SpreadingFactor, TxConfig};
17use lorawan_device::async_device::Timings;
23 18
24#[derive(Debug, Copy, Clone)] 19#[derive(Debug, Copy, Clone)]
25#[cfg_attr(feature = "defmt", derive(defmt::Format))] 20#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -98,9 +93,7 @@ impl<'a> StateInner<'a> {
98 self.radio.set_standby(StandbyClk::Rc)?; 93 self.radio.set_standby(StandbyClk::Rc)?;
99 let tcxo_mode = TcxoMode::new() 94 let tcxo_mode = TcxoMode::new()
100 .set_txco_trim(TcxoTrim::Volts1pt7) 95 .set_txco_trim(TcxoTrim::Volts1pt7)
101 .set_timeout(Timeout::from_duration_sat( 96 .set_timeout(Timeout::from_duration_sat(core::time::Duration::from_millis(40)));
102 core::time::Duration::from_millis(40),
103 ));
104 97
105 self.radio.set_tcxo_mode(&tcxo_mode)?; 98 self.radio.set_tcxo_mode(&tcxo_mode)?;
106 self.radio.set_regulator_mode(RegMode::Ldo)?; 99 self.radio.set_regulator_mode(RegMode::Ldo)?;
@@ -109,21 +102,14 @@ impl<'a> StateInner<'a> {
109 102
110 self.radio.set_buffer_base_address(0, 0)?; 103 self.radio.set_buffer_base_address(0, 0)?;
111 104
112 self.radio.set_pa_config( 105 self.radio
113 &PaConfig::new() 106 .set_pa_config(&PaConfig::new().set_pa_duty_cycle(0x1).set_hp_max(0x0).set_pa(PaSel::Lp))?;
114 .set_pa_duty_cycle(0x1)
115 .set_hp_max(0x0)
116 .set_pa(PaSel::Lp),
117 )?;
118 107
119 self.radio.set_pa_ocp(Ocp::Max140m)?; 108 self.radio.set_pa_ocp(Ocp::Max140m)?;
120 109
121 // let tx_params = TxParams::LP_14.set_ramp_time(RampTime::Micros40); 110 // let tx_params = TxParams::LP_14.set_ramp_time(RampTime::Micros40);
122 self.radio.set_tx_params( 111 self.radio
123 &TxParams::new() 112 .set_tx_params(&TxParams::new().set_ramp_time(RampTime::Micros40).set_power(0x0A))?;
124 .set_ramp_time(RampTime::Micros40)
125 .set_power(0x0A),
126 )?;
127 113
128 self.radio.set_packet_type(PacketType::LoRa)?; 114 self.radio.set_packet_type(PacketType::LoRa)?;
129 self.radio.set_lora_sync_word(LoRaSyncWord::Public)?; 115 self.radio.set_lora_sync_word(LoRaSyncWord::Public)?;
@@ -193,19 +179,14 @@ impl<'a> StateInner<'a> {
193 179
194 /// Perform a radio receive operation with the radio config and receive buffer. The receive buffer must 180 /// Perform a radio receive operation with the radio config and receive buffer. The receive buffer must
195 /// be able to hold a single LoRaWAN packet. 181 /// be able to hold a single LoRaWAN packet.
196 async fn do_rx( 182 async fn do_rx(&mut self, config: RfConfig, buf: &mut [u8]) -> Result<(usize, RxQuality), RadioError> {
197 &mut self,
198 config: RfConfig,
199 buf: &mut [u8],
200 ) -> Result<(usize, RxQuality), RadioError> {
201 assert!(buf.len() >= 255); 183 assert!(buf.len() >= 255);
202 trace!("RX START"); 184 trace!("RX START");
203 // trace!("Starting RX: {}", config); 185 // trace!("Starting RX: {}", config);
204 self.switch.set_rx(); 186 self.switch.set_rx();
205 self.configure()?; 187 self.configure()?;
206 188
207 self.radio 189 self.radio.set_rf_frequency(&RfFreq::from_frequency(config.frequency))?;
208 .set_rf_frequency(&RfFreq::from_frequency(config.frequency))?;
209 190
210 let mod_params = LoRaModParams::new() 191 let mod_params = LoRaModParams::new()
211 .set_sf(convert_spreading_factor(config.spreading_factor)) 192 .set_sf(convert_spreading_factor(config.spreading_factor))
@@ -315,16 +296,8 @@ pub struct RadioSwitch<'a> {
315} 296}
316 297
317impl<'a> RadioSwitch<'a> { 298impl<'a> RadioSwitch<'a> {
318 pub fn new( 299 pub fn new(ctrl1: Output<'a, AnyPin>, ctrl2: Output<'a, AnyPin>, ctrl3: Output<'a, AnyPin>) -> Self {
319 ctrl1: Output<'a, AnyPin>, 300 Self { ctrl1, ctrl2, ctrl3 }
320 ctrl2: Output<'a, AnyPin>,
321 ctrl3: Output<'a, AnyPin>,
322 ) -> Self {
323 Self {
324 ctrl1,
325 ctrl2,
326 ctrl3,
327 }
328 } 301 }
329 302
330 pub(crate) fn set_rx(&mut self) { 303 pub(crate) fn set_rx(&mut self) {
diff --git a/embassy-lora/src/sx127x/mod.rs b/embassy-lora/src/sx127x/mod.rs
index c70f33582..f47a9eb55 100644
--- a/embassy-lora/src/sx127x/mod.rs
+++ b/embassy-lora/src/sx127x/mod.rs
@@ -1,11 +1,10 @@
1use core::future::Future; 1use core::future::Future;
2
2use embedded_hal::digital::v2::OutputPin; 3use embedded_hal::digital::v2::OutputPin;
3use embedded_hal_async::digital::Wait; 4use embedded_hal_async::digital::Wait;
4use embedded_hal_async::spi::*; 5use embedded_hal_async::spi::*;
5use lorawan_device::async_device::{ 6use lorawan_device::async_device::radio::{Bandwidth, PhyRxTx, RfConfig, RxQuality, SpreadingFactor, TxConfig};
6 radio::{Bandwidth, PhyRxTx, RfConfig, RxQuality, SpreadingFactor, TxConfig}, 7use lorawan_device::async_device::Timings;
7 Timings,
8};
9 8
10mod sx127x_lora; 9mod sx127x_lora;
11use sx127x_lora::{Error as RadioError, LoRa, RadioMode, IRQ}; 10use sx127x_lora::{Error as RadioError, LoRa, RadioMode, IRQ};
diff --git a/embassy-lora/src/sx127x/sx127x_lora/mod.rs b/embassy-lora/src/sx127x/sx127x_lora/mod.rs
index 62eaf0a95..8b937ec2f 100644
--- a/embassy-lora/src/sx127x/sx127x_lora/mod.rs
+++ b/embassy-lora/src/sx127x/sx127x_lora/mod.rs
@@ -11,9 +11,8 @@ use embedded_hal::digital::v2::OutputPin;
11use embedded_hal_async::spi::SpiBus; 11use embedded_hal_async::spi::SpiBus;
12 12
13mod register; 13mod register;
14use self::register::PaConfig;
15use self::register::Register;
16pub use self::register::IRQ; 14pub use self::register::IRQ;
15use self::register::{PaConfig, Register};
17 16
18/// Provides high-level access to Semtech SX1276/77/78/79 based boards connected to a Raspberry Pi 17/// Provides high-level access to Semtech SX1276/77/78/79 based boards connected to a Raspberry Pi
19pub struct LoRa<SPI, CS, RESET> { 18pub struct LoRa<SPI, CS, RESET> {
@@ -72,15 +71,11 @@ where
72 let version = self.read_register(Register::RegVersion.addr()).await?; 71 let version = self.read_register(Register::RegVersion.addr()).await?;
73 if version == VERSION_CHECK { 72 if version == VERSION_CHECK {
74 self.set_mode(RadioMode::Sleep).await?; 73 self.set_mode(RadioMode::Sleep).await?;
75 self.write_register(Register::RegFifoTxBaseAddr.addr(), 0) 74 self.write_register(Register::RegFifoTxBaseAddr.addr(), 0).await?;
76 .await?; 75 self.write_register(Register::RegFifoRxBaseAddr.addr(), 0).await?;
77 self.write_register(Register::RegFifoRxBaseAddr.addr(), 0)
78 .await?;
79 let lna = self.read_register(Register::RegLna.addr()).await?; 76 let lna = self.read_register(Register::RegLna.addr()).await?;
80 self.write_register(Register::RegLna.addr(), lna | 0x03) 77 self.write_register(Register::RegLna.addr(), lna | 0x03).await?;
81 .await?; 78 self.write_register(Register::RegModemConfig3.addr(), 0x04).await?;
82 self.write_register(Register::RegModemConfig3.addr(), 0x04)
83 .await?;
84 self.set_tcxo(true).await?; 79 self.set_tcxo(true).await?;
85 self.set_mode(RadioMode::Stdby).await?; 80 self.set_mode(RadioMode::Stdby).await?;
86 self.cs.set_high().map_err(CS)?; 81 self.cs.set_high().map_err(CS)?;
@@ -106,10 +101,7 @@ where
106 .await 101 .await
107 } 102 }
108 103
109 pub async fn transmit_start( 104 pub async fn transmit_start(&mut self, buffer: &[u8]) -> Result<(), Error<E, CS::Error, RESET::Error>> {
110 &mut self,
111 buffer: &[u8],
112 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
113 assert!(buffer.len() < 255); 105 assert!(buffer.len() < 255);
114 if self.transmitting().await? { 106 if self.transmitting().await? {
115 //trace!("ALREADY TRANSMNITTING"); 107 //trace!("ALREADY TRANSMNITTING");
@@ -123,10 +115,8 @@ where
123 } 115 }
124 116
125 self.write_register(Register::RegIrqFlags.addr(), 0).await?; 117 self.write_register(Register::RegIrqFlags.addr(), 0).await?;
126 self.write_register(Register::RegFifoAddrPtr.addr(), 0) 118 self.write_register(Register::RegFifoAddrPtr.addr(), 0).await?;
127 .await?; 119 self.write_register(Register::RegPayloadLength.addr(), 0).await?;
128 self.write_register(Register::RegPayloadLength.addr(), 0)
129 .await?;
130 for byte in buffer.iter() { 120 for byte in buffer.iter() {
131 self.write_register(Register::RegFifo.addr(), *byte).await?; 121 self.write_register(Register::RegFifo.addr(), *byte).await?;
132 } 122 }
@@ -138,10 +128,7 @@ where
138 } 128 }
139 129
140 pub async fn packet_ready(&mut self) -> Result<bool, Error<E, CS::Error, RESET::Error>> { 130 pub async fn packet_ready(&mut self) -> Result<bool, Error<E, CS::Error, RESET::Error>> {
141 Ok(self 131 Ok(self.read_register(Register::RegIrqFlags.addr()).await?.get_bit(6))
142 .read_register(Register::RegIrqFlags.addr())
143 .await?
144 .get_bit(6))
145 } 132 }
146 133
147 pub async fn irq_flags_mask(&mut self) -> Result<u8, Error<E, CS::Error, RESET::Error>> { 134 pub async fn irq_flags_mask(&mut self) -> Result<u8, Error<E, CS::Error, RESET::Error>> {
@@ -159,37 +146,26 @@ where
159 146
160 /// Returns the contents of the fifo as a fixed 255 u8 array. This should only be called is there is a 147 /// Returns the contents of the fifo as a fixed 255 u8 array. This should only be called is there is a
161 /// new packet ready to be read. 148 /// new packet ready to be read.
162 pub async fn read_packet( 149 pub async fn read_packet(&mut self, buffer: &mut [u8]) -> Result<(), Error<E, CS::Error, RESET::Error>> {
163 &mut self,
164 buffer: &mut [u8],
165 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
166 self.clear_irq().await?; 150 self.clear_irq().await?;
167 let size = self.read_register(Register::RegRxNbBytes.addr()).await?; 151 let size = self.read_register(Register::RegRxNbBytes.addr()).await?;
168 assert!(size as usize <= buffer.len()); 152 assert!(size as usize <= buffer.len());
169 let fifo_addr = self 153 let fifo_addr = self.read_register(Register::RegFifoRxCurrentAddr.addr()).await?;
170 .read_register(Register::RegFifoRxCurrentAddr.addr()) 154 self.write_register(Register::RegFifoAddrPtr.addr(), fifo_addr).await?;
171 .await?;
172 self.write_register(Register::RegFifoAddrPtr.addr(), fifo_addr)
173 .await?;
174 for i in 0..size { 155 for i in 0..size {
175 let byte = self.read_register(Register::RegFifo.addr()).await?; 156 let byte = self.read_register(Register::RegFifo.addr()).await?;
176 buffer[i as usize] = byte; 157 buffer[i as usize] = byte;
177 } 158 }
178 self.write_register(Register::RegFifoAddrPtr.addr(), 0) 159 self.write_register(Register::RegFifoAddrPtr.addr(), 0).await?;
179 .await?;
180 Ok(()) 160 Ok(())
181 } 161 }
182 162
183 /// Returns true if the radio is currently transmitting a packet. 163 /// Returns true if the radio is currently transmitting a packet.
184 pub async fn transmitting(&mut self) -> Result<bool, Error<E, CS::Error, RESET::Error>> { 164 pub async fn transmitting(&mut self) -> Result<bool, Error<E, CS::Error, RESET::Error>> {
185 if (self.read_register(Register::RegOpMode.addr()).await?) & RadioMode::Tx.addr() 165 if (self.read_register(Register::RegOpMode.addr()).await?) & RadioMode::Tx.addr() == RadioMode::Tx.addr() {
186 == RadioMode::Tx.addr()
187 {
188 Ok(true) 166 Ok(true)
189 } else { 167 } else {
190 if (self.read_register(Register::RegIrqFlags.addr()).await? & IRQ::IrqTxDoneMask.addr()) 168 if (self.read_register(Register::RegIrqFlags.addr()).await? & IRQ::IrqTxDoneMask.addr()) == 1 {
191 == 1
192 {
193 self.write_register(Register::RegIrqFlags.addr(), IRQ::IrqTxDoneMask.addr()) 169 self.write_register(Register::RegIrqFlags.addr(), IRQ::IrqTxDoneMask.addr())
194 .await?; 170 .await?;
195 } 171 }
@@ -200,8 +176,7 @@ where
200 /// Clears the radio's IRQ registers. 176 /// Clears the radio's IRQ registers.
201 pub async fn clear_irq(&mut self) -> Result<u8, Error<E, CS::Error, RESET::Error>> { 177 pub async fn clear_irq(&mut self) -> Result<u8, Error<E, CS::Error, RESET::Error>> {
202 let irq_flags = self.read_register(Register::RegIrqFlags.addr()).await?; 178 let irq_flags = self.read_register(Register::RegIrqFlags.addr()).await?;
203 self.write_register(Register::RegIrqFlags.addr(), 0xFF) 179 self.write_register(Register::RegIrqFlags.addr(), 0xFF).await?;
204 .await?;
205 Ok(irq_flags) 180 Ok(irq_flags)
206 } 181 }
207 182
@@ -243,11 +218,8 @@ where
243 self.set_ocp(100).await?; 218 self.set_ocp(100).await?;
244 } 219 }
245 level -= 2; 220 level -= 2;
246 self.write_register( 221 self.write_register(Register::RegPaConfig.addr(), PaConfig::PaBoost.addr() | level as u8)
247 Register::RegPaConfig.addr(), 222 .await
248 PaConfig::PaBoost.addr() | level as u8,
249 )
250 .await
251 } 223 }
252 } 224 }
253 225
@@ -269,10 +241,7 @@ where
269 } 241 }
270 242
271 /// Sets the state of the radio. Default mode after initiation is `Standby`. 243 /// Sets the state of the radio. Default mode after initiation is `Standby`.
272 pub async fn set_mode( 244 pub async fn set_mode(&mut self, mode: RadioMode) -> Result<(), Error<E, CS::Error, RESET::Error>> {
273 &mut self,
274 mode: RadioMode,
275 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
276 if self.explicit_header { 245 if self.explicit_header {
277 self.set_explicit_header_mode().await?; 246 self.set_explicit_header_mode().await?;
278 } else { 247 } else {
@@ -289,25 +258,18 @@ where
289 } 258 }
290 259
291 pub async fn reset_payload_length(&mut self) -> Result<(), Error<E, CS::Error, RESET::Error>> { 260 pub async fn reset_payload_length(&mut self) -> Result<(), Error<E, CS::Error, RESET::Error>> {
292 self.write_register(Register::RegPayloadLength.addr(), 0xFF) 261 self.write_register(Register::RegPayloadLength.addr(), 0xFF).await
293 .await
294 } 262 }
295 263
296 /// Sets the frequency of the radio. Values are in megahertz. 264 /// Sets the frequency of the radio. Values are in megahertz.
297 /// I.E. 915 MHz must be used for North America. Check regulation for your area. 265 /// I.E. 915 MHz must be used for North America. Check regulation for your area.
298 pub async fn set_frequency( 266 pub async fn set_frequency(&mut self, freq: u32) -> Result<(), Error<E, CS::Error, RESET::Error>> {
299 &mut self,
300 freq: u32,
301 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
302 const FREQ_STEP: f64 = 61.03515625; 267 const FREQ_STEP: f64 = 61.03515625;
303 // calculate register values 268 // calculate register values
304 let frf = (freq as f64 / FREQ_STEP) as u32; 269 let frf = (freq as f64 / FREQ_STEP) as u32;
305 // write registers 270 // write registers
306 self.write_register( 271 self.write_register(Register::RegFrfMsb.addr(), ((frf & 0x00FF_0000) >> 16) as u8)
307 Register::RegFrfMsb.addr(), 272 .await?;
308 ((frf & 0x00FF_0000) >> 16) as u8,
309 )
310 .await?;
311 self.write_register(Register::RegFrfMid.addr(), ((frf & 0x0000_FF00) >> 8) as u8) 273 self.write_register(Register::RegFrfMid.addr(), ((frf & 0x0000_FF00) >> 8) as u8)
312 .await?; 274 .await?;
313 self.write_register(Register::RegFrfLsb.addr(), (frf & 0x0000_00FF) as u8) 275 self.write_register(Register::RegFrfLsb.addr(), (frf & 0x0000_00FF) as u8)
@@ -335,10 +297,7 @@ where
335 /// Sets the spreading factor of the radio. Supported values are between 6 and 12. 297 /// Sets the spreading factor of the radio. Supported values are between 6 and 12.
336 /// If a spreading factor of 6 is set, implicit header mode must be used to transmit 298 /// If a spreading factor of 6 is set, implicit header mode must be used to transmit
337 /// and receive packets. Default value is `7`. 299 /// and receive packets. Default value is `7`.
338 pub async fn set_spreading_factor( 300 pub async fn set_spreading_factor(&mut self, mut sf: u8) -> Result<(), Error<E, CS::Error, RESET::Error>> {
339 &mut self,
340 mut sf: u8,
341 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
342 if sf < 6 { 301 if sf < 6 {
343 sf = 6; 302 sf = 6;
344 } else if sf > 12 { 303 } else if sf > 12 {
@@ -346,13 +305,11 @@ where
346 } 305 }
347 306
348 if sf == 6 { 307 if sf == 6 {
349 self.write_register(Register::RegDetectionOptimize.addr(), 0xc5) 308 self.write_register(Register::RegDetectionOptimize.addr(), 0xc5).await?;
350 .await?;
351 self.write_register(Register::RegDetectionThreshold.addr(), 0x0c) 309 self.write_register(Register::RegDetectionThreshold.addr(), 0x0c)
352 .await?; 310 .await?;
353 } else { 311 } else {
354 self.write_register(Register::RegDetectionOptimize.addr(), 0xc3) 312 self.write_register(Register::RegDetectionOptimize.addr(), 0xc3).await?;
355 .await?;
356 self.write_register(Register::RegDetectionThreshold.addr(), 0x0a) 313 self.write_register(Register::RegDetectionThreshold.addr(), 0x0a)
357 .await?; 314 .await?;
358 } 315 }
@@ -364,16 +321,12 @@ where
364 .await?; 321 .await?;
365 self.set_ldo_flag().await?; 322 self.set_ldo_flag().await?;
366 323
367 self.write_register(Register::RegSymbTimeoutLsb.addr(), 0x05) 324 self.write_register(Register::RegSymbTimeoutLsb.addr(), 0x05).await?;
368 .await?;
369 325
370 Ok(()) 326 Ok(())
371 } 327 }
372 328
373 pub async fn set_tcxo( 329 pub async fn set_tcxo(&mut self, external: bool) -> Result<(), Error<E, CS::Error, RESET::Error>> {
374 &mut self,
375 external: bool,
376 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
377 if external { 330 if external {
378 self.write_register(Register::RegTcxo.addr(), 0x10).await 331 self.write_register(Register::RegTcxo.addr(), 0x10).await
379 } else { 332 } else {
@@ -384,10 +337,7 @@ where
384 /// Sets the signal bandwidth of the radio. Supported values are: `7800 Hz`, `10400 Hz`, 337 /// Sets the signal bandwidth of the radio. Supported values are: `7800 Hz`, `10400 Hz`,
385 /// `15600 Hz`, `20800 Hz`, `31250 Hz`,`41700 Hz` ,`62500 Hz`,`125000 Hz` and `250000 Hz` 338 /// `15600 Hz`, `20800 Hz`, `31250 Hz`,`41700 Hz` ,`62500 Hz`,`125000 Hz` and `250000 Hz`
386 /// Default value is `125000 Hz` 339 /// Default value is `125000 Hz`
387 pub async fn set_signal_bandwidth( 340 pub async fn set_signal_bandwidth(&mut self, sbw: i64) -> Result<(), Error<E, CS::Error, RESET::Error>> {
388 &mut self,
389 sbw: i64,
390 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
391 let bw: i64 = match sbw { 341 let bw: i64 = match sbw {
392 7_800 => 0, 342 7_800 => 0,
393 10_400 => 1, 343 10_400 => 1,
@@ -413,10 +363,7 @@ where
413 /// Sets the coding rate of the radio with the numerator fixed at 4. Supported values 363 /// Sets the coding rate of the radio with the numerator fixed at 4. Supported values
414 /// are between `5` and `8`, these correspond to coding rates of `4/5` and `4/8`. 364 /// are between `5` and `8`, these correspond to coding rates of `4/5` and `4/8`.
415 /// Default value is `5`. 365 /// Default value is `5`.
416 pub async fn set_coding_rate_4( 366 pub async fn set_coding_rate_4(&mut self, mut denominator: u8) -> Result<(), Error<E, CS::Error, RESET::Error>> {
417 &mut self,
418 mut denominator: u8,
419 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
420 if denominator < 5 { 367 if denominator < 5 {
421 denominator = 5; 368 denominator = 5;
422 } else if denominator > 8 { 369 } else if denominator > 8 {
@@ -424,23 +371,16 @@ where
424 } 371 }
425 let cr = denominator - 4; 372 let cr = denominator - 4;
426 let modem_config_1 = self.read_register(Register::RegModemConfig1.addr()).await?; 373 let modem_config_1 = self.read_register(Register::RegModemConfig1.addr()).await?;
427 self.write_register( 374 self.write_register(Register::RegModemConfig1.addr(), (modem_config_1 & 0xf1) | (cr << 1))
428 Register::RegModemConfig1.addr(), 375 .await
429 (modem_config_1 & 0xf1) | (cr << 1),
430 )
431 .await
432 } 376 }
433 377
434 /// Sets the preamble length of the radio. Values are between 6 and 65535. 378 /// Sets the preamble length of the radio. Values are between 6 and 65535.
435 /// Default value is `8`. 379 /// Default value is `8`.
436 pub async fn set_preamble_length( 380 pub async fn set_preamble_length(&mut self, length: i64) -> Result<(), Error<E, CS::Error, RESET::Error>> {
437 &mut self,
438 length: i64,
439 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
440 self.write_register(Register::RegPreambleMsb.addr(), (length >> 8) as u8) 381 self.write_register(Register::RegPreambleMsb.addr(), (length >> 8) as u8)
441 .await?; 382 .await?;
442 self.write_register(Register::RegPreambleLsb.addr(), length as u8) 383 self.write_register(Register::RegPreambleLsb.addr(), length as u8).await
443 .await
444 } 384 }
445 385
446 /// Enables are disables the radio's CRC check. Default value is `false`. 386 /// Enables are disables the radio's CRC check. Default value is `false`.
@@ -456,20 +396,13 @@ where
456 } 396 }
457 397
458 /// Inverts the radio's IQ signals. Default value is `false`. 398 /// Inverts the radio's IQ signals. Default value is `false`.
459 pub async fn set_invert_iq( 399 pub async fn set_invert_iq(&mut self, value: bool) -> Result<(), Error<E, CS::Error, RESET::Error>> {
460 &mut self,
461 value: bool,
462 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
463 if value { 400 if value {
464 self.write_register(Register::RegInvertiq.addr(), 0x66) 401 self.write_register(Register::RegInvertiq.addr(), 0x66).await?;
465 .await?; 402 self.write_register(Register::RegInvertiq2.addr(), 0x19).await
466 self.write_register(Register::RegInvertiq2.addr(), 0x19)
467 .await
468 } else { 403 } else {
469 self.write_register(Register::RegInvertiq.addr(), 0x27) 404 self.write_register(Register::RegInvertiq.addr(), 0x27).await?;
470 .await?; 405 self.write_register(Register::RegInvertiq2.addr(), 0x1d).await
471 self.write_register(Register::RegInvertiq2.addr(), 0x1d)
472 .await
473 } 406 }
474 } 407 }
475 408
@@ -504,15 +437,11 @@ where
504 437
505 /// Returns the signal to noise radio of the the last received packet. 438 /// Returns the signal to noise radio of the the last received packet.
506 pub async fn get_packet_snr(&mut self) -> Result<f64, Error<E, CS::Error, RESET::Error>> { 439 pub async fn get_packet_snr(&mut self) -> Result<f64, Error<E, CS::Error, RESET::Error>> {
507 Ok(f64::from( 440 Ok(f64::from(self.read_register(Register::RegPktSnrValue.addr()).await?))
508 self.read_register(Register::RegPktSnrValue.addr()).await?,
509 ))
510 } 441 }
511 442
512 /// Returns the frequency error of the last received packet in Hz. 443 /// Returns the frequency error of the last received packet in Hz.
513 pub async fn get_packet_frequency_error( 444 pub async fn get_packet_frequency_error(&mut self) -> Result<i64, Error<E, CS::Error, RESET::Error>> {
514 &mut self,
515 ) -> Result<i64, Error<E, CS::Error, RESET::Error>> {
516 let mut freq_error: i32; 445 let mut freq_error: i32;
517 freq_error = i32::from(self.read_register(Register::RegFreqErrorMsb.addr()).await? & 0x7); 446 freq_error = i32::from(self.read_register(Register::RegFreqErrorMsb.addr()).await? & 0x7);
518 freq_error <<= 8i64; 447 freq_error <<= 8i64;
@@ -537,29 +466,20 @@ where
537 let mut config_3 = self.read_register(Register::RegModemConfig3.addr()).await?; 466 let mut config_3 = self.read_register(Register::RegModemConfig3.addr()).await?;
538 config_3.set_bit(3, ldo_on); 467 config_3.set_bit(3, ldo_on);
539 //config_3.set_bit(2, true); 468 //config_3.set_bit(2, true);
540 self.write_register(Register::RegModemConfig3.addr(), config_3) 469 self.write_register(Register::RegModemConfig3.addr(), config_3).await
541 .await
542 } 470 }
543 471
544 async fn read_register(&mut self, reg: u8) -> Result<u8, Error<E, CS::Error, RESET::Error>> { 472 async fn read_register(&mut self, reg: u8) -> Result<u8, Error<E, CS::Error, RESET::Error>> {
545 let mut buffer = [reg & 0x7f, 0]; 473 let mut buffer = [reg & 0x7f, 0];
546 self.cs.set_low().map_err(CS)?; 474 self.cs.set_low().map_err(CS)?;
547 475
548 let _ = self 476 let _ = self.spi.transfer(&mut buffer, &[reg & 0x7f, 0]).await.map_err(SPI)?;
549 .spi
550 .transfer(&mut buffer, &[reg & 0x7f, 0])
551 .await
552 .map_err(SPI)?;
553 477
554 self.cs.set_high().map_err(CS)?; 478 self.cs.set_high().map_err(CS)?;
555 Ok(buffer[1]) 479 Ok(buffer[1])
556 } 480 }
557 481
558 async fn write_register( 482 async fn write_register(&mut self, reg: u8, byte: u8) -> Result<(), Error<E, CS::Error, RESET::Error>> {
559 &mut self,
560 reg: u8,
561 byte: u8,
562 ) -> Result<(), Error<E, CS::Error, RESET::Error>> {
563 self.cs.set_low().map_err(CS)?; 483 self.cs.set_low().map_err(CS)?;
564 let buffer = [reg | 0x80, byte]; 484 let buffer = [reg | 0x80, byte];
565 self.spi.write(&buffer).await.map_err(SPI)?; 485 self.spi.write(&buffer).await.map_err(SPI)?;
@@ -576,8 +496,7 @@ where
576 .set_bit(3, false) //Low freq registers 496 .set_bit(3, false) //Low freq registers
577 .set_bits(0..2, 0b011); // Mode 497 .set_bits(0..2, 0b011); // Mode
578 498
579 self.write_register(Register::RegOpMode as u8, op_mode) 499 self.write_register(Register::RegOpMode as u8, op_mode).await
580 .await
581 } 500 }
582 501
583 pub async fn set_fsk_pa_ramp( 502 pub async fn set_fsk_pa_ramp(
@@ -590,8 +509,7 @@ where
590 .set_bits(5..6, modulation_shaping as u8) 509 .set_bits(5..6, modulation_shaping as u8)
591 .set_bits(0..3, ramp as u8); 510 .set_bits(0..3, ramp as u8);
592 511
593 self.write_register(Register::RegPaRamp as u8, pa_ramp) 512 self.write_register(Register::RegPaRamp as u8, pa_ramp).await
594 .await
595 } 513 }
596 514
597 pub async fn set_lora_pa_ramp(&mut self) -> Result<(), Error<E, CS::Error, RESET::Error>> { 515 pub async fn set_lora_pa_ramp(&mut self) -> Result<(), Error<E, CS::Error, RESET::Error>> {