diff options
| author | Felipe Balbi <[email protected]> | 2025-12-18 10:14:36 -0800 |
|---|---|---|
| committer | Felipe Balbi <[email protected]> | 2025-12-18 10:14:36 -0800 |
| commit | 743295b1e9836016827c635877ecd8870b2620c3 (patch) | |
| tree | 69f4215c6f891ad92dfd2adfdfa228a89c6eeb4f /embassy-mcxa/src/dma.rs | |
| parent | c3b5b1243f9ac80c85dc2fd1f88788a60baafd2f (diff) | |
[MCXA] dma: fix typo
Should be an and, not or.
Diffstat (limited to 'embassy-mcxa/src/dma.rs')
| -rw-r--r-- | embassy-mcxa/src/dma.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-mcxa/src/dma.rs b/embassy-mcxa/src/dma.rs index 8d519d99b..b68f55e65 100644 --- a/embassy-mcxa/src/dma.rs +++ b/embassy-mcxa/src/dma.rs | |||
| @@ -1924,7 +1924,7 @@ impl Iterator for TransferErrorRawIter { | |||
| 1924 | 1924 | ||
| 1925 | for (mask, var) in TransferErrorRaw::MAP { | 1925 | for (mask, var) in TransferErrorRaw::MAP { |
| 1926 | // If the bit is set... | 1926 | // If the bit is set... |
| 1927 | if self.0 | mask != 0 { | 1927 | if self.0 & mask != 0 { |
| 1928 | // clear the bit | 1928 | // clear the bit |
| 1929 | self.0 &= !mask; | 1929 | self.0 &= !mask; |
| 1930 | // and return the answer | 1930 | // and return the answer |