diff options
| author | James Munns <[email protected]> | 2025-12-05 14:57:25 +0100 |
|---|---|---|
| committer | James Munns <[email protected]> | 2025-12-05 14:57:25 +0100 |
| commit | 1ce2083f9a0fcf1cfbb10de0fb3ed44b460a5cc7 (patch) | |
| tree | cb561beff31634841c1b1c67e31da74a449336a6 /embassy-mcxa/src | |
| parent | 273b996efe489b285f2da6ab6e2ad8077463a576 (diff) | |
Enable DMA interrupts in constructors
Diffstat (limited to 'embassy-mcxa/src')
| -rw-r--r-- | embassy-mcxa/src/lpuart/mod.rs | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/embassy-mcxa/src/lpuart/mod.rs b/embassy-mcxa/src/lpuart/mod.rs index 6e60164e6..39fecb413 100644 --- a/embassy-mcxa/src/lpuart/mod.rs +++ b/embassy-mcxa/src/lpuart/mod.rs | |||
| @@ -1187,10 +1187,14 @@ impl<'a, T: Instance, C: DmaChannelTrait> LpuartTxDma<'a, T, C> { | |||
| 1187 | // Initialize LPUART with TX enabled, RX disabled, no flow control | 1187 | // Initialize LPUART with TX enabled, RX disabled, no flow control |
| 1188 | Lpuart::<Async>::init::<T>(true, false, false, false, config)?; | 1188 | Lpuart::<Async>::init::<T>(true, false, false, false, config)?; |
| 1189 | 1189 | ||
| 1190 | // Enable interrupt | ||
| 1191 | let tx_dma = DmaChannel::new(tx_dma_ch); | ||
| 1192 | tx_dma.enable_interrupt(); | ||
| 1193 | |||
| 1190 | Ok(Self { | 1194 | Ok(Self { |
| 1191 | info: T::info(), | 1195 | info: T::info(), |
| 1192 | _tx_pin: tx_pin, | 1196 | _tx_pin: tx_pin, |
| 1193 | tx_dma: DmaChannel::new(tx_dma_ch), | 1197 | tx_dma, |
| 1194 | _instance: core::marker::PhantomData, | 1198 | _instance: core::marker::PhantomData, |
| 1195 | }) | 1199 | }) |
| 1196 | } | 1200 | } |
| @@ -1299,10 +1303,14 @@ impl<'a, T: Instance, C: DmaChannelTrait> LpuartRxDma<'a, T, C> { | |||
| 1299 | // Initialize LPUART with TX disabled, RX enabled, no flow control | 1303 | // Initialize LPUART with TX disabled, RX enabled, no flow control |
| 1300 | Lpuart::<Async>::init::<T>(false, true, false, false, config)?; | 1304 | Lpuart::<Async>::init::<T>(false, true, false, false, config)?; |
| 1301 | 1305 | ||
| 1306 | // Enable dma interrupt | ||
| 1307 | let rx_dma = DmaChannel::new(rx_dma_ch); | ||
| 1308 | rx_dma.enable_interrupt(); | ||
| 1309 | |||
| 1302 | Ok(Self { | 1310 | Ok(Self { |
| 1303 | info: T::info(), | 1311 | info: T::info(), |
| 1304 | _rx_pin: rx_pin, | 1312 | _rx_pin: rx_pin, |
| 1305 | rx_dma: DmaChannel::new(rx_dma_ch), | 1313 | rx_dma, |
| 1306 | _instance: core::marker::PhantomData, | 1314 | _instance: core::marker::PhantomData, |
| 1307 | }) | 1315 | }) |
| 1308 | } | 1316 | } |
| @@ -1476,17 +1484,23 @@ impl<'a, T: Instance, TxC: DmaChannelTrait, RxC: DmaChannelTrait> LpuartDma<'a, | |||
| 1476 | // Initialize LPUART with both TX and RX enabled, no flow control | 1484 | // Initialize LPUART with both TX and RX enabled, no flow control |
| 1477 | Lpuart::<Async>::init::<T>(true, true, false, false, config)?; | 1485 | Lpuart::<Async>::init::<T>(true, true, false, false, config)?; |
| 1478 | 1486 | ||
| 1487 | // Enable DMA interrupts | ||
| 1488 | let tx_dma = DmaChannel::new(tx_dma_ch); | ||
| 1489 | let rx_dma = DmaChannel::new(rx_dma_ch); | ||
| 1490 | tx_dma.enable_interrupt(); | ||
| 1491 | rx_dma.enable_interrupt(); | ||
| 1492 | |||
| 1479 | Ok(Self { | 1493 | Ok(Self { |
| 1480 | tx: LpuartTxDma { | 1494 | tx: LpuartTxDma { |
| 1481 | info: T::info(), | 1495 | info: T::info(), |
| 1482 | _tx_pin: tx_pin, | 1496 | _tx_pin: tx_pin, |
| 1483 | tx_dma: DmaChannel::new(tx_dma_ch), | 1497 | tx_dma, |
| 1484 | _instance: core::marker::PhantomData, | 1498 | _instance: core::marker::PhantomData, |
| 1485 | }, | 1499 | }, |
| 1486 | rx: LpuartRxDma { | 1500 | rx: LpuartRxDma { |
| 1487 | info: T::info(), | 1501 | info: T::info(), |
| 1488 | _rx_pin: rx_pin, | 1502 | _rx_pin: rx_pin, |
| 1489 | rx_dma: DmaChannel::new(rx_dma_ch), | 1503 | rx_dma, |
| 1490 | _instance: core::marker::PhantomData, | 1504 | _instance: core::marker::PhantomData, |
| 1491 | }, | 1505 | }, |
| 1492 | }) | 1506 | }) |
