Clean up examples, move interrupts to be more fully managed

2 files changed, 21 insertions, 72 deletions

diff --git a/embassy-mcxa/src/dma.rs b/embassy-mcxa/src/dma.rs
index b3ea94dbf..07500e9a2 100644
--- a/embassy-mcxa/src/dma.rs
+++ b/embassy-mcxa/src/dma.rs
@@ -618,16 +618,9 @@ impl<C: Channel> DmaChannel<C> {
     /// Note: DMA is initialized during `hal::init()` via `dma::init()`.
     #[inline]
     pub fn new(_ch: embassy_hal_internal::Peri<'_, C>) -> Self {
-        Self {
-            _ch: core::marker::PhantomData,
+        unsafe {
+            cortex_m::peripheral::NVIC::unmask(C::INTERRUPT);
         }
-    }
-
-    /// Wrap a DMA channel token directly (for internal use).
-    ///
-    /// Note: DMA is initialized during `hal::init()` via `dma::init()`.
-    #[inline]
-    pub fn from_token(_ch: C) -> Self {
         Self {
             _ch: core::marker::PhantomData,
         }
@@ -740,7 +733,8 @@ impl<C: Channel> DmaChannel<C> {
     #[inline]
     fn set_even_transfer_size(t: &'static pac::edma_0_tcd0::Tcd, sz: WordSize) {
         let hw_size = sz.to_hw_size();
-        t.tcd_attr().write(|w| unsafe { w.ssize().bits(hw_size).dsize().bits(hw_size) } );
+        t.tcd_attr()
+            .write(|w| unsafe { w.ssize().bits(hw_size).dsize().bits(hw_size) });
     }
 
     #[inline]
@@ -1068,7 +1062,7 @@ impl<C: Channel> DmaChannel<C> {
 
         // Addresses
         Self::set_source_ptr(t, buf.as_ptr());
-        t.tcd_daddr().write(|w| w.daddr().bits(peri_addr as u32));
+        Self::set_dest_ptr(t, peri_addr);
 
         // Offsets: Source increments, Dest fixed
         Self::set_source_increment(t, size);
@@ -2357,7 +2351,7 @@ impl<W: Word> ScatterGatherBuilder<W> {
 
         // Reset channel state - clear DONE, disable requests, clear errors
         // This ensures the channel is in a clean state before loading the TCD
-        Self::reset_channel_state(t);
+        DmaChannel::<C>::reset_channel_state(t);
 
         // Memory barrier to ensure channel state is reset before loading TCD
         cortex_m::asm::dsb();
@@ -2441,38 +2435,28 @@ pub unsafe fn on_interrupt(ch_index: usize) {
 }
 
 // ============================================================================
-// Type-level Interrupt Handlers for bind_interrupts! macro
+// Type-level Interrupt Handlers
 // ============================================================================
 
 /// Macro to generate DMA channel interrupt handlers.
-///
-/// This generates handler structs that implement the `Handler` trait for use
-/// with the `bind_interrupts!` macro.
 macro_rules! impl_dma_interrupt_handler {
-    ($name:ident, $irq:ident, $ch:expr) => {
-        /// Interrupt handler for DMA channel.
-        ///
-        /// Use this with the `bind_interrupts!` macro:
-        /// ```ignore
-        /// bind_interrupts!(struct Irqs {
-        #[doc = concat!("     ", stringify!($irq), " => dma::", stringify!($name), ";")]
-        /// });
-        /// ```
-        pub struct $name;
-
-        impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::$irq> for $name {
-            unsafe fn on_interrupt() {
+    ($irq:ident, $ch:expr) => {
+        #[interrupt]
+        fn $irq() {
+            unsafe {
                 on_interrupt($ch);
             }
         }
     };
 }
 
-impl_dma_interrupt_handler!(DmaCh0InterruptHandler, DMA_CH0, 0);
-impl_dma_interrupt_handler!(DmaCh1InterruptHandler, DMA_CH1, 1);
-impl_dma_interrupt_handler!(DmaCh2InterruptHandler, DMA_CH2, 2);
-impl_dma_interrupt_handler!(DmaCh3InterruptHandler, DMA_CH3, 3);
-impl_dma_interrupt_handler!(DmaCh4InterruptHandler, DMA_CH4, 4);
-impl_dma_interrupt_handler!(DmaCh5InterruptHandler, DMA_CH5, 5);
-impl_dma_interrupt_handler!(DmaCh6InterruptHandler, DMA_CH6, 6);
-impl_dma_interrupt_handler!(DmaCh7InterruptHandler, DMA_CH7, 7);
+use crate::pac::interrupt;
+
+impl_dma_interrupt_handler!(DMA_CH0, 0);
+impl_dma_interrupt_handler!(DMA_CH1, 1);
+impl_dma_interrupt_handler!(DMA_CH2, 2);
+impl_dma_interrupt_handler!(DMA_CH3, 3);
+impl_dma_interrupt_handler!(DMA_CH4, 4);
+impl_dma_interrupt_handler!(DMA_CH5, 5);
+impl_dma_interrupt_handler!(DMA_CH6, 6);
+impl_dma_interrupt_handler!(DMA_CH7, 7);
diff --git a/embassy-mcxa/src/lib.rs b/embassy-mcxa/src/lib.rs
index 23cda7511..724f99234 100644
--- a/embassy-mcxa/src/lib.rs
+++ b/embassy-mcxa/src/lib.rs
@@ -400,41 +400,6 @@ pub fn init(cfg: crate::config::Config) -> Peripherals {
     peripherals
 }
 
-// /// Optional hook called by cortex-m-rt before RAM init.
-// /// We proactively mask and clear all NVIC IRQs to avoid wedges from stale state
-// /// left by soft resets/debug sessions.
-// ///
-// /// NOTE: Manual VTOR setup is required for RAM execution. The cortex-m-rt 'set-vtor'
-// /// feature is incompatible with our setup because it expects __vector_table to be
-// /// defined differently than how our RAM-based linker script arranges it.
-// #[no_mangle]
-// pub unsafe extern "C" fn __pre_init() {
-//     // Set the VTOR to point to the interrupt vector table in RAM
-//     // This is required since code runs from RAM on this MCU
-//     crate::interrupt::vtor_set_ram_vector_base(0x2000_0000 as *const u32);
-
-//     // Mask and clear pending for all NVIC lines (0..127) to avoid stale state across runs.
-//     let nvic = &*cortex_m::peripheral::NVIC::PTR;
-//     for i in 0..4 {
-//         // 4 words x 32 = 128 IRQs
-//         nvic.icer[i].write(0xFFFF_FFFF);
-//         nvic.icpr[i].write(0xFFFF_FFFF);
-//     }
-//     // Do NOT touch peripheral registers here: clocks may be off and accesses can fault.
-//     crate::interrupt::clear_default_handler_snapshot();
-// }
-
-/// Internal helper to dispatch a type-level interrupt handler.
-#[inline(always)]
-#[doc(hidden)]
-pub unsafe fn __handle_interrupt<T, H>()
-where
-    T: crate::interrupt::typelevel::Interrupt,
-    H: crate::interrupt::typelevel::Handler<T>,
-{
-    H::on_interrupt();
-}
-
 /// Macro to bind interrupts to handlers, similar to embassy-imxrt.
 ///
 /// Example: