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authorJames Munns <[email protected]>2025-12-11 16:34:11 +0000
committerGitHub <[email protected]>2025-12-11 16:34:11 +0000
commit9a12d8dd5be520f44536106743ba50adafcd2b80 (patch)
tree7ca8137d64cb4f33158d998ecb02cfdac626ae90 /embassy-mcxa
parent933eb5b63d0a479a99d95da9111500be35966f4b (diff)
parentc4855d254fdfa3f06583b0883f603fee0615bd41 (diff)
Merge pull request #5040 from jamesmunns/james/cleanup-reexports
[MCXA]: Remove some unusual top level re-exports
Diffstat (limited to 'embassy-mcxa')
-rw-r--r--embassy-mcxa/src/i2c/controller.rs2
-rw-r--r--embassy-mcxa/src/lib.rs3
-rw-r--r--embassy-mcxa/src/lpuart/mod.rs4
3 files changed, 4 insertions, 5 deletions
diff --git a/embassy-mcxa/src/i2c/controller.rs b/embassy-mcxa/src/i2c/controller.rs
index c27d508b0..62789f85f 100644
--- a/embassy-mcxa/src/i2c/controller.rs
+++ b/embassy-mcxa/src/i2c/controller.rs
@@ -8,9 +8,9 @@ use embassy_hal_internal::drop::OnDrop;
8use mcxa_pac::lpi2c0::mtdr::Cmd; 8use mcxa_pac::lpi2c0::mtdr::Cmd;
9 9
10use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin}; 10use super::{Async, Blocking, Error, Instance, InterruptHandler, Mode, Result, SclPin, SdaPin};
11use crate::AnyPin;
12use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig}; 11use crate::clocks::periph_helpers::{Div4, Lpi2cClockSel, Lpi2cConfig};
13use crate::clocks::{PoweredClock, enable_and_reset}; 12use crate::clocks::{PoweredClock, enable_and_reset};
13use crate::gpio::AnyPin;
14use crate::interrupt::typelevel::Interrupt; 14use crate::interrupt::typelevel::Interrupt;
15 15
16/// Bus speed (nominal SCL, no clock stretching) 16/// Bus speed (nominal SCL, no clock stretching)
diff --git a/embassy-mcxa/src/lib.rs b/embassy-mcxa/src/lib.rs
index 7de5839be..22bc40e35 100644
--- a/embassy-mcxa/src/lib.rs
+++ b/embassy-mcxa/src/lib.rs
@@ -20,6 +20,7 @@ pub mod ostimer;
20pub mod reset_reason; 20pub mod reset_reason;
21pub mod rtc; 21pub mod rtc;
22 22
23use crate::interrupt::InterruptExt;
23pub use crate::pac::NVIC_PRIO_BITS; 24pub use crate::pac::NVIC_PRIO_BITS;
24 25
25#[rustfmt::skip] 26#[rustfmt::skip]
@@ -338,8 +339,6 @@ embassy_hal_internal::peripherals!(
338// Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it. 339// Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it.
339 340
340// Re-export interrupt traits and types 341// Re-export interrupt traits and types
341pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output};
342pub use interrupt::InterruptExt;
343#[cfg(feature = "unstable-pac")] 342#[cfg(feature = "unstable-pac")]
344pub use mcxa_pac as pac; 343pub use mcxa_pac as pac;
345#[cfg(not(feature = "unstable-pac"))] 344#[cfg(not(feature = "unstable-pac"))]
diff --git a/embassy-mcxa/src/lpuart/mod.rs b/embassy-mcxa/src/lpuart/mod.rs
index e59ce8140..bce3986b5 100644
--- a/embassy-mcxa/src/lpuart/mod.rs
+++ b/embassy-mcxa/src/lpuart/mod.rs
@@ -6,12 +6,12 @@ use paste::paste;
6 6
7use crate::clocks::periph_helpers::{Div4, LpuartClockSel, LpuartConfig}; 7use crate::clocks::periph_helpers::{Div4, LpuartClockSel, LpuartConfig};
8use crate::clocks::{ClockError, Gate, PoweredClock, enable_and_reset}; 8use crate::clocks::{ClockError, Gate, PoweredClock, enable_and_reset};
9use crate::gpio::SealedPin; 9use crate::gpio::{AnyPin, SealedPin};
10use crate::pac::lpuart0::baud::Sbns as StopBits; 10use crate::pac::lpuart0::baud::Sbns as StopBits;
11use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, M as DataBits, Pt as Parity}; 11use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, M as DataBits, Pt as Parity};
12use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; 12use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource};
13use crate::pac::lpuart0::stat::Msbf as MsbFirst; 13use crate::pac::lpuart0::stat::Msbf as MsbFirst;
14use crate::{AnyPin, interrupt, pac}; 14use crate::{interrupt, pac};
15 15
16pub mod buffered; 16pub mod buffered;
17 17