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authorDario Nieuwenhuis <[email protected]>2023-08-12 03:07:13 +0200
committerDario Nieuwenhuis <[email protected]>2023-08-15 14:09:36 +0200
commit253b28debaf13d839087a2b9160f416f4be22438 (patch)
treeb5c731f15a26bf7516f1be850faaec2a3ec8a2b3 /embassy-net-enc28j60/src
parent4af1cf88d29f29df52f8c9e7928409e60a91ffbc (diff)
net-enc28j60: fix PHY read unreliable due to missing dummy byte.
Diffstat (limited to 'embassy-net-enc28j60/src')
-rw-r--r--embassy-net-enc28j60/src/lib.rs19
-rw-r--r--embassy-net-enc28j60/src/phy.rs3
2 files changed, 13 insertions, 9 deletions
diff --git a/embassy-net-enc28j60/src/lib.rs b/embassy-net-enc28j60/src/lib.rs
index 4f129b6b2..d77dc2c5e 100644
--- a/embassy-net-enc28j60/src/lib.rs
+++ b/embassy-net-enc28j60/src/lib.rs
@@ -361,10 +361,16 @@ where
361 fn _read_control_register(&mut self, register: Register) -> u8 { 361 fn _read_control_register(&mut self, register: Register) -> u8 {
362 self.change_bank(register); 362 self.change_bank(register);
363 363
364 let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0]; 364 if register.is_eth_register() {
365 self.spi.transfer_in_place(&mut buffer).unwrap(); 365 let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0];
366 366 self.spi.transfer_in_place(&mut buffer).unwrap();
367 buffer[1] 367 buffer[1]
368 } else {
369 // MAC, MII regs need a dummy byte.
370 let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0, 0];
371 self.spi.transfer_in_place(&mut buffer).unwrap();
372 buffer[2]
373 }
368 } 374 }
369 375
370 fn read_phy_register(&mut self, register: phy::Register) -> u16 { 376 fn read_phy_register(&mut self, register: phy::Register) -> u16 {
@@ -379,11 +385,10 @@ where
379 // wait until the read operation finishes 385 // wait until the read operation finishes
380 while self.read_control_register(bank3::Register::MISTAT) & 0b1 != 0 {} 386 while self.read_control_register(bank3::Register::MISTAT) & 0b1 != 0 {}
381 387
382 let h = self.read_control_register(bank2::Register::MIRDH);
383 let l = self.read_control_register(bank2::Register::MIRDL);
384
385 self.write_control_register(bank2::Register::MICMD, bank2::MICMD::default().miird(0).bits()); 388 self.write_control_register(bank2::Register::MICMD, bank2::MICMD::default().miird(0).bits());
386 389
390 let l = self.read_control_register(bank2::Register::MIRDL);
391 let h = self.read_control_register(bank2::Register::MIRDH);
387 (l as u16) | (h as u16) << 8 392 (l as u16) | (h as u16) << 8
388 } 393 }
389 394
diff --git a/embassy-net-enc28j60/src/phy.rs b/embassy-net-enc28j60/src/phy.rs
index 7f62b5f27..89144ada3 100644
--- a/embassy-net-enc28j60/src/phy.rs
+++ b/embassy-net-enc28j60/src/phy.rs
@@ -30,7 +30,6 @@ register!(PHCON2, 0, u16, {
30}); 30});
31 31
32register!(PHSTAT2, 0, u16, { 32register!(PHSTAT2, 0, u16, {
33 // Datasheet says it's bit 10, but it's actually bit 2 ?!?!
34 #[doc = "Link Status bit"] 33 #[doc = "Link Status bit"]
35 lstat @ 2, 34 lstat @ 10,
36}); 35});