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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2022-04-12 21:42:36 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2022-04-12 21:42:36 +0000 |
| commit | 6d0e6d563dfd900a56ee6b6b3cf48a2af53c6cd4 (patch) | |
| tree | b92b609e8a6323a3d4c88cd4eef6b2ff22e313df /embassy-net/src/stack.rs | |
| parent | 5d48153bd752af283ced3621aa7e75ed6a67a0a2 (diff) | |
| parent | 8f6fccf012f76ba264042381b351f874735ca35e (diff) | |
Merge #714
714: add more clock options for l4 and l5 r=Dirbaio a=ant32
- added an assert so it panics if pll48div is not 48Mhz
- added MSI as a clock source for PLL
- removed hsi48 option for MCUs mentioned in l4 rcc presentation
- copied some code from l4 to l5, but don't have a way of testing it.
Co-authored-by: Philip A Reimer <[email protected]>
Diffstat (limited to 'embassy-net/src/stack.rs')
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