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authorDario Nieuwenhuis <[email protected]>2022-02-12 01:04:01 +0100
committerDario Nieuwenhuis <[email protected]>2022-02-12 01:07:02 +0100
commit6de02bb23e270141885e24719dc8fbca0bb97feb (patch)
tree01d6d2d13c3df50fff429ec06190ef27ac412e3f /embassy-nrf/src/buffered_uarte.rs
parent5ae4e20f8654bdc129d152b5364b6864457c2e02 (diff)
nrf: remove OptionalPin
Diffstat (limited to 'embassy-nrf/src/buffered_uarte.rs')
-rw-r--r--embassy-nrf/src/buffered_uarte.rs24
1 files changed, 7 insertions, 17 deletions
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 2880c84f6..b49c12788 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -27,8 +27,7 @@ use embassy_hal_common::peripheral::{PeripheralMutex, PeripheralState, StateStor
27use embassy_hal_common::ring_buffer::RingBuffer; 27use embassy_hal_common::ring_buffer::RingBuffer;
28use embassy_hal_common::{low_power_wait_until, unborrow}; 28use embassy_hal_common::{low_power_wait_until, unborrow};
29 29
30use crate::gpio::sealed::Pin as _; 30use crate::gpio::Pin as GpioPin;
31use crate::gpio::{OptionalPin as GpioOptionalPin, Pin as GpioPin};
32use crate::pac; 31use crate::pac;
33use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task}; 32use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
34use crate::timer::Instance as TimerInstance; 33use crate::timer::Instance as TimerInstance;
@@ -89,8 +88,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
89 irq: impl Unborrow<Target = U::Interrupt> + 'd, 88 irq: impl Unborrow<Target = U::Interrupt> + 'd,
90 rxd: impl Unborrow<Target = impl GpioPin> + 'd, 89 rxd: impl Unborrow<Target = impl GpioPin> + 'd,
91 txd: impl Unborrow<Target = impl GpioPin> + 'd, 90 txd: impl Unborrow<Target = impl GpioPin> + 'd,
92 cts: impl Unborrow<Target = impl GpioOptionalPin> + 'd, 91 cts: impl Unborrow<Target = impl GpioPin> + 'd,
93 rts: impl Unborrow<Target = impl GpioOptionalPin> + 'd, 92 rts: impl Unborrow<Target = impl GpioPin> + 'd,
94 config: Config, 93 config: Config,
95 rx_buffer: &'d mut [u8], 94 rx_buffer: &'d mut [u8],
96 tx_buffer: &'d mut [u8], 95 tx_buffer: &'d mut [u8],
@@ -108,28 +107,19 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
108 txd.conf().write(|w| w.dir().output().drive().h0h1()); 107 txd.conf().write(|w| w.dir().output().drive().h0h1());
109 r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) }); 108 r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
110 109
111 if let Some(pin) = rts.pin_mut() { 110 cts.conf().write(|w| w.input().connect().drive().h0h1());
112 pin.set_high();
113 pin.conf().write(|w| w.dir().output().drive().h0h1());
114 }
115 r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) }); 111 r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
116 112
117 if let Some(pin) = cts.pin_mut() { 113 rts.set_high();
118 pin.conf().write(|w| w.input().connect().drive().h0h1()); 114 rts.conf().write(|w| w.dir().output().drive().h0h1());
119 }
120 r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) }); 115 r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
121 116
122 r.baudrate.write(|w| w.baudrate().variant(config.baudrate)); 117 r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
123 r.config.write(|w| w.parity().variant(config.parity)); 118 r.config.write(|w| w.parity().variant(config.parity));
124 119
125 // Configure 120 // Configure
126 let hardware_flow_control = match (rts.pin().is_some(), cts.pin().is_some()) {
127 (false, false) => false,
128 (true, true) => true,
129 _ => panic!("RTS and CTS pins must be either both set or none set."),
130 };
131 r.config.write(|w| { 121 r.config.write(|w| {
132 w.hwfc().bit(hardware_flow_control); 122 w.hwfc().bit(true);
133 w.parity().variant(config.parity); 123 w.parity().variant(config.parity);
134 w 124 w
135 }); 125 });