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authorDario Nieuwenhuis <[email protected]>2024-06-17 22:50:13 +0200
committerDario Nieuwenhuis <[email protected]>2024-06-25 23:18:16 +0200
commitc48547b475eb039a9d30f4c1e03d0c9f65cdec18 (patch)
treeb4f389f2f13b96d9aca2f9bcd59cac26342251b8 /embassy-nrf/src/buffered_uarte.rs
parente4c4036a46218b3ba4bde28e4e056a439ac7055b (diff)
nrf: fix wrong order configuring gpios.
Docs say "PSEL.RXD, PSEL.RTS, PSEL.RTS, and PSEL.TXD must only be configured when the UARTE is disabled." For some reason nrf52 doesn't care but nrf91 does.
Diffstat (limited to 'embassy-nrf/src/buffered_uarte.rs')
-rw-r--r--embassy-nrf/src/buffered_uarte.rs3
1 files changed, 3 insertions, 0 deletions
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 385d4015e..071c18760 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -304,6 +304,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
304 let tx = BufferedUarteTx::new_innerer(unsafe { peri.clone_unchecked() }, txd, cts, tx_buffer); 304 let tx = BufferedUarteTx::new_innerer(unsafe { peri.clone_unchecked() }, txd, cts, tx_buffer);
305 let rx = BufferedUarteRx::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer); 305 let rx = BufferedUarteRx::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
306 306
307 U::regs().enable.write(|w| w.enable().enabled());
307 U::Interrupt::pend(); 308 U::Interrupt::pend();
308 unsafe { U::Interrupt::enable() }; 309 unsafe { U::Interrupt::enable() };
309 310
@@ -405,6 +406,7 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
405 406
406 let this = Self::new_innerer(peri, txd, cts, tx_buffer); 407 let this = Self::new_innerer(peri, txd, cts, tx_buffer);
407 408
409 U::regs().enable.write(|w| w.enable().enabled());
408 U::Interrupt::pend(); 410 U::Interrupt::pend();
409 unsafe { U::Interrupt::enable() }; 411 unsafe { U::Interrupt::enable() };
410 412
@@ -602,6 +604,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
602 604
603 let this = Self::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer); 605 let this = Self::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
604 606
607 U::regs().enable.write(|w| w.enable().enabled());
605 U::Interrupt::pend(); 608 U::Interrupt::pend();
606 unsafe { U::Interrupt::enable() }; 609 unsafe { U::Interrupt::enable() };
607 610