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authorMichael Gomez <[email protected]>2025-03-19 20:44:16 -0700
committerMichael Gomez <[email protected]>2025-04-04 21:54:36 -0700
commitf1feedf19031d0c007628569add51ff89ae08447 (patch)
treeb9ecb4c4e809115a9e8cd8a7bc4cae293dbfc713 /embassy-nrf/src/buffered_uarte.rs
parenta44abaf7e4562fa5393087fd845bf0d02141325b (diff)
BufferedUart initialization
This change modifies UART initialization throughout Embassy to take pins before interrupts. Related to #1304.
Diffstat (limited to 'embassy-nrf/src/buffered_uarte.rs')
-rw-r--r--embassy-nrf/src/buffered_uarte.rs10
1 files changed, 5 insertions, 5 deletions
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index f939be004..29e126903 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -227,9 +227,9 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
227 ppi_ch1: Peri<'d, impl ConfigurableChannel>, 227 ppi_ch1: Peri<'d, impl ConfigurableChannel>,
228 ppi_ch2: Peri<'d, impl ConfigurableChannel>, 228 ppi_ch2: Peri<'d, impl ConfigurableChannel>,
229 ppi_group: Peri<'d, impl Group>, 229 ppi_group: Peri<'d, impl Group>,
230 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
231 rxd: Peri<'d, impl GpioPin>, 230 rxd: Peri<'d, impl GpioPin>,
232 txd: Peri<'d, impl GpioPin>, 231 txd: Peri<'d, impl GpioPin>,
232 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
233 config: Config, 233 config: Config,
234 rx_buffer: &'d mut [u8], 234 rx_buffer: &'d mut [u8],
235 tx_buffer: &'d mut [u8], 235 tx_buffer: &'d mut [u8],
@@ -262,11 +262,11 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
262 ppi_ch1: Peri<'d, impl ConfigurableChannel>, 262 ppi_ch1: Peri<'d, impl ConfigurableChannel>,
263 ppi_ch2: Peri<'d, impl ConfigurableChannel>, 263 ppi_ch2: Peri<'d, impl ConfigurableChannel>,
264 ppi_group: Peri<'d, impl Group>, 264 ppi_group: Peri<'d, impl Group>,
265 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
266 rxd: Peri<'d, impl GpioPin>, 265 rxd: Peri<'d, impl GpioPin>,
267 txd: Peri<'d, impl GpioPin>, 266 txd: Peri<'d, impl GpioPin>,
268 cts: Peri<'d, impl GpioPin>, 267 cts: Peri<'d, impl GpioPin>,
269 rts: Peri<'d, impl GpioPin>, 268 rts: Peri<'d, impl GpioPin>,
269 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
270 config: Config, 270 config: Config,
271 rx_buffer: &'d mut [u8], 271 rx_buffer: &'d mut [u8],
272 tx_buffer: &'d mut [u8], 272 tx_buffer: &'d mut [u8],
@@ -377,8 +377,8 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
377 /// Create a new BufferedUarteTx without hardware flow control. 377 /// Create a new BufferedUarteTx without hardware flow control.
378 pub fn new( 378 pub fn new(
379 uarte: Peri<'d, U>, 379 uarte: Peri<'d, U>,
380 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
381 txd: Peri<'d, impl GpioPin>, 380 txd: Peri<'d, impl GpioPin>,
381 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
382 config: Config, 382 config: Config,
383 tx_buffer: &'d mut [u8], 383 tx_buffer: &'d mut [u8],
384 ) -> Self { 384 ) -> Self {
@@ -392,9 +392,9 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
392 /// Panics if `rx_buffer.len()` is odd. 392 /// Panics if `rx_buffer.len()` is odd.
393 pub fn new_with_cts( 393 pub fn new_with_cts(
394 uarte: Peri<'d, U>, 394 uarte: Peri<'d, U>,
395 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
396 txd: Peri<'d, impl GpioPin>, 395 txd: Peri<'d, impl GpioPin>,
397 cts: Peri<'d, impl GpioPin>, 396 cts: Peri<'d, impl GpioPin>,
397 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
398 config: Config, 398 config: Config,
399 tx_buffer: &'d mut [u8], 399 tx_buffer: &'d mut [u8],
400 ) -> Self { 400 ) -> Self {
@@ -588,9 +588,9 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
588 ppi_ch1: Peri<'d, impl ConfigurableChannel>, 588 ppi_ch1: Peri<'d, impl ConfigurableChannel>,
589 ppi_ch2: Peri<'d, impl ConfigurableChannel>, 589 ppi_ch2: Peri<'d, impl ConfigurableChannel>,
590 ppi_group: Peri<'d, impl Group>, 590 ppi_group: Peri<'d, impl Group>,
591 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
592 rxd: Peri<'d, impl GpioPin>, 591 rxd: Peri<'d, impl GpioPin>,
593 rts: Peri<'d, impl GpioPin>, 592 rts: Peri<'d, impl GpioPin>,
593 _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
594 config: Config, 594 config: Config,
595 rx_buffer: &'d mut [u8], 595 rx_buffer: &'d mut [u8],
596 ) -> Self { 596 ) -> Self {