aboutsummaryrefslogtreecommitdiff
path: root/embassy-nrf/src/chips/nrf52832.rs
diff options
context:
space:
mode:
authorgoueslati <[email protected]>2023-06-12 14:27:53 +0100
committergoueslati <[email protected]>2023-06-12 14:27:53 +0100
commit2d89cfb18f00aefbfa108728dfea3398e80ea3e4 (patch)
tree6485dacac7e61c4378ac522e709edb0a86bd7523 /embassy-nrf/src/chips/nrf52832.rs
parent2dd5ce83ec0421564e85b667f5dabd592f313e5c (diff)
parentab86b060500ceda1c80e39f35af69cb08a7b63a2 (diff)
fix merge conflict
Diffstat (limited to 'embassy-nrf/src/chips/nrf52832.rs')
-rw-r--r--embassy-nrf/src/chips/nrf52832.rs82
1 files changed, 39 insertions, 43 deletions
diff --git a/embassy-nrf/src/chips/nrf52832.rs b/embassy-nrf/src/chips/nrf52832.rs
index 83ecd0deb..b77564a5c 100644
--- a/embassy-nrf/src/chips/nrf52832.rs
+++ b/embassy-nrf/src/chips/nrf52832.rs
@@ -263,46 +263,42 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
263 263
264impl_i2s!(I2S, I2S, I2S); 264impl_i2s!(I2S, I2S, I2S);
265 265
266pub mod irqs { 266embassy_hal_common::interrupt_mod!(
267 use embassy_cortex_m::interrupt::_export::declare; 267 POWER_CLOCK,
268 268 RADIO,
269 use crate::pac::Interrupt as InterruptEnum; 269 UARTE0_UART0,
270 270 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
271 declare!(POWER_CLOCK); 271 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
272 declare!(RADIO); 272 NFCT,
273 declare!(UARTE0_UART0); 273 GPIOTE,
274 declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 274 SAADC,
275 declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 275 TIMER0,
276 declare!(NFCT); 276 TIMER1,
277 declare!(GPIOTE); 277 TIMER2,
278 declare!(SAADC); 278 RTC0,
279 declare!(TIMER0); 279 TEMP,
280 declare!(TIMER1); 280 RNG,
281 declare!(TIMER2); 281 ECB,
282 declare!(RTC0); 282 CCM_AAR,
283 declare!(TEMP); 283 WDT,
284 declare!(RNG); 284 RTC1,
285 declare!(ECB); 285 QDEC,
286 declare!(CCM_AAR); 286 COMP_LPCOMP,
287 declare!(WDT); 287 SWI0_EGU0,
288 declare!(RTC1); 288 SWI1_EGU1,
289 declare!(QDEC); 289 SWI2_EGU2,
290 declare!(COMP_LPCOMP); 290 SWI3_EGU3,
291 declare!(SWI0_EGU0); 291 SWI4_EGU4,
292 declare!(SWI1_EGU1); 292 SWI5_EGU5,
293 declare!(SWI2_EGU2); 293 TIMER3,
294 declare!(SWI3_EGU3); 294 TIMER4,
295 declare!(SWI4_EGU4); 295 PWM0,
296 declare!(SWI5_EGU5); 296 PDM,
297 declare!(TIMER3); 297 MWU,
298 declare!(TIMER4); 298 PWM1,
299 declare!(PWM0); 299 PWM2,
300 declare!(PDM); 300 SPIM2_SPIS2_SPI2,
301 declare!(MWU); 301 RTC2,
302 declare!(PWM1); 302 FPU,
303 declare!(PWM2); 303 I2S,
304 declare!(SPIM2_SPIS2_SPI2); 304);
305 declare!(RTC2);
306 declare!(FPU);
307 declare!(I2S);
308}