diff options
| author | goueslati <[email protected]> | 2023-06-12 14:27:53 +0100 |
|---|---|---|
| committer | goueslati <[email protected]> | 2023-06-12 14:27:53 +0100 |
| commit | 2d89cfb18f00aefbfa108728dfea3398e80ea3e4 (patch) | |
| tree | 6485dacac7e61c4378ac522e709edb0a86bd7523 /embassy-nrf/src/chips/nrf52840.rs | |
| parent | 2dd5ce83ec0421564e85b667f5dabd592f313e5c (diff) | |
| parent | ab86b060500ceda1c80e39f35af69cb08a7b63a2 (diff) | |
fix merge conflict
Diffstat (limited to 'embassy-nrf/src/chips/nrf52840.rs')
| -rw-r--r-- | embassy-nrf/src/chips/nrf52840.rs | 94 |
1 files changed, 45 insertions, 49 deletions
diff --git a/embassy-nrf/src/chips/nrf52840.rs b/embassy-nrf/src/chips/nrf52840.rs index f6d33f85c..9b0050823 100644 --- a/embassy-nrf/src/chips/nrf52840.rs +++ b/embassy-nrf/src/chips/nrf52840.rs | |||
| @@ -311,52 +311,48 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7); | |||
| 311 | 311 | ||
| 312 | impl_i2s!(I2S, I2S, I2S); | 312 | impl_i2s!(I2S, I2S, I2S); |
| 313 | 313 | ||
| 314 | pub mod irqs { | 314 | embassy_hal_common::interrupt_mod!( |
| 315 | use embassy_cortex_m::interrupt::_export::declare; | 315 | POWER_CLOCK, |
| 316 | 316 | RADIO, | |
| 317 | use crate::pac::Interrupt as InterruptEnum; | 317 | UARTE0_UART0, |
| 318 | 318 | SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, | |
| 319 | declare!(POWER_CLOCK); | 319 | SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, |
| 320 | declare!(RADIO); | 320 | NFCT, |
| 321 | declare!(UARTE0_UART0); | 321 | GPIOTE, |
| 322 | declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | 322 | SAADC, |
| 323 | declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | 323 | TIMER0, |
| 324 | declare!(NFCT); | 324 | TIMER1, |
| 325 | declare!(GPIOTE); | 325 | TIMER2, |
| 326 | declare!(SAADC); | 326 | RTC0, |
| 327 | declare!(TIMER0); | 327 | TEMP, |
| 328 | declare!(TIMER1); | 328 | RNG, |
| 329 | declare!(TIMER2); | 329 | ECB, |
| 330 | declare!(RTC0); | 330 | CCM_AAR, |
| 331 | declare!(TEMP); | 331 | WDT, |
| 332 | declare!(RNG); | 332 | RTC1, |
| 333 | declare!(ECB); | 333 | QDEC, |
| 334 | declare!(CCM_AAR); | 334 | COMP_LPCOMP, |
| 335 | declare!(WDT); | 335 | SWI0_EGU0, |
| 336 | declare!(RTC1); | 336 | SWI1_EGU1, |
| 337 | declare!(QDEC); | 337 | SWI2_EGU2, |
| 338 | declare!(COMP_LPCOMP); | 338 | SWI3_EGU3, |
| 339 | declare!(SWI0_EGU0); | 339 | SWI4_EGU4, |
| 340 | declare!(SWI1_EGU1); | 340 | SWI5_EGU5, |
| 341 | declare!(SWI2_EGU2); | 341 | TIMER3, |
| 342 | declare!(SWI3_EGU3); | 342 | TIMER4, |
| 343 | declare!(SWI4_EGU4); | 343 | PWM0, |
| 344 | declare!(SWI5_EGU5); | 344 | PDM, |
| 345 | declare!(TIMER3); | 345 | MWU, |
| 346 | declare!(TIMER4); | 346 | PWM1, |
| 347 | declare!(PWM0); | 347 | PWM2, |
| 348 | declare!(PDM); | 348 | SPIM2_SPIS2_SPI2, |
| 349 | declare!(MWU); | 349 | RTC2, |
| 350 | declare!(PWM1); | 350 | FPU, |
| 351 | declare!(PWM2); | 351 | USBD, |
| 352 | declare!(SPIM2_SPIS2_SPI2); | 352 | UARTE1, |
| 353 | declare!(RTC2); | 353 | QSPI, |
| 354 | declare!(FPU); | 354 | CRYPTOCELL, |
| 355 | declare!(USBD); | 355 | PWM3, |
| 356 | declare!(UARTE1); | 356 | SPIM3, |
| 357 | declare!(QSPI); | 357 | I2S, |
| 358 | declare!(CRYPTOCELL); | 358 | ); |
| 359 | declare!(PWM3); | ||
| 360 | declare!(SPIM3); | ||
| 361 | declare!(I2S); | ||
| 362 | } | ||
