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authorDario Nieuwenhuis <[email protected]>2020-12-29 15:32:23 +0100
committerGitHub <[email protected]>2020-12-29 15:32:23 +0100
commit2bf9b14ef07c4d2a33ee8a45b2f07b4cdd050e9e (patch)
tree8229727035f1aa26a9477fa702f02dd53592dd99 /embassy-nrf/src/interrupt.rs
parentb01a88a839c2ac1eec68442f6cddf0c0a887cfa7 (diff)
parent7dc81faa4ec46074c3500a868df18e0d123f0ba6 (diff)
Merge pull request #7 from akiles/irq
Owned IRQs
Diffstat (limited to 'embassy-nrf/src/interrupt.rs')
-rw-r--r--embassy-nrf/src/interrupt.rs250
1 files changed, 201 insertions, 49 deletions
diff --git a/embassy-nrf/src/interrupt.rs b/embassy-nrf/src/interrupt.rs
index 17fc9ab34..90b568573 100644
--- a/embassy-nrf/src/interrupt.rs
+++ b/embassy-nrf/src/interrupt.rs
@@ -5,12 +5,13 @@
5 5
6use core::sync::atomic::{compiler_fence, Ordering}; 6use core::sync::atomic::{compiler_fence, Ordering};
7 7
8use crate::pac::{NVIC, NVIC_PRIO_BITS}; 8use crate::pac::NVIC_PRIO_BITS;
9 9
10// Re-exports 10// Re-exports
11pub use crate::pac::Interrupt; 11pub use crate::pac::Interrupt;
12pub use crate::pac::Interrupt::*; // needed for cortex-m-rt #[interrupt] 12pub use crate::pac::Interrupt::*; // needed for cortex-m-rt #[interrupt]
13pub use cortex_m::interrupt::{CriticalSection, Mutex}; 13pub use cortex_m::interrupt::{CriticalSection, Mutex};
14pub use embassy::interrupt::{declare, take, OwnedInterrupt};
14 15
15#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 16#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
16#[cfg_attr(feature = "defmt", derive(defmt::Format))] 17#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -26,14 +27,8 @@ pub enum Priority {
26 Level7 = 7, 27 Level7 = 7,
27} 28}
28 29
29impl Priority { 30impl From<u8> for Priority {
30 #[inline] 31 fn from(priority: u8) -> Self {
31 fn to_nvic(self) -> u8 {
32 (self as u8) << (8 - NVIC_PRIO_BITS)
33 }
34
35 #[inline]
36 fn from_nvic(priority: u8) -> Self {
37 match priority >> (8 - NVIC_PRIO_BITS) { 32 match priority >> (8 - NVIC_PRIO_BITS) {
38 0 => Self::Level0, 33 0 => Self::Level0,
39 1 => Self::Level1, 34 1 => Self::Level1,
@@ -48,6 +43,12 @@ impl Priority {
48 } 43 }
49} 44}
50 45
46impl From<Priority> for u8 {
47 fn from(p: Priority) -> Self {
48 (p as u8) << (8 - NVIC_PRIO_BITS)
49 }
50}
51
51#[inline] 52#[inline]
52pub fn free<F, R>(f: F) -> R 53pub fn free<F, R>(f: F) -> R
53where 54where
@@ -77,53 +78,204 @@ where
77 } 78 }
78} 79}
79 80
80#[inline] 81#[cfg(feature = "52810")]
81pub fn enable(irq: Interrupt) { 82mod irqs {
82 unsafe { 83 use super::*;
83 NVIC::unmask(irq); 84 declare!(POWER_CLOCK);
84 } 85 declare!(RADIO);
86 declare!(UARTE0_UART0);
87 declare!(TWIM0_TWIS0_TWI0);
88 declare!(SPIM0_SPIS0_SPI0);
89 declare!(GPIOTE);
90 declare!(SAADC);
91 declare!(TIMER0);
92 declare!(TIMER1);
93 declare!(TIMER2);
94 declare!(RTC0);
95 declare!(TEMP);
96 declare!(RNG);
97 declare!(ECB);
98 declare!(CCM_AAR);
99 declare!(WDT);
100 declare!(RTC1);
101 declare!(QDEC);
102 declare!(COMP);
103 declare!(SWI0_EGU0);
104 declare!(SWI1_EGU1);
105 declare!(SWI2);
106 declare!(SWI3);
107 declare!(SWI4);
108 declare!(SWI5);
109 declare!(PWM0);
110 declare!(PDM);
85} 111}
86 112
87#[inline] 113#[cfg(feature = "52811")]
88pub fn disable(irq: Interrupt) { 114mod irqs {
89 NVIC::mask(irq); 115 use super::*;
116 declare!(POWER_CLOCK);
117 declare!(RADIO);
118 declare!(UARTE0_UART0);
119 declare!(TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1);
120 declare!(SPIM0_SPIS0_SPI0);
121 declare!(GPIOTE);
122 declare!(SAADC);
123 declare!(TIMER0);
124 declare!(TIMER1);
125 declare!(TIMER2);
126 declare!(RTC0);
127 declare!(TEMP);
128 declare!(RNG);
129 declare!(ECB);
130 declare!(CCM_AAR);
131 declare!(WDT);
132 declare!(RTC1);
133 declare!(QDEC);
134 declare!(COMP);
135 declare!(SWI0_EGU0);
136 declare!(SWI1_EGU1);
137 declare!(SWI2);
138 declare!(SWI3);
139 declare!(SWI4);
140 declare!(SWI5);
141 declare!(PWM0);
142 declare!(PDM);
90} 143}
91 144
92#[inline] 145#[cfg(feature = "52832")]
93pub fn is_active(irq: Interrupt) -> bool { 146mod irqs {
94 NVIC::is_active(irq) 147 use super::*;
148 declare!(POWER_CLOCK);
149 declare!(RADIO);
150 declare!(UARTE0_UART0);
151 declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
152 declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
153 declare!(NFCT);
154 declare!(GPIOTE);
155 declare!(SAADC);
156 declare!(TIMER0);
157 declare!(TIMER1);
158 declare!(TIMER2);
159 declare!(RTC0);
160 declare!(TEMP);
161 declare!(RNG);
162 declare!(ECB);
163 declare!(CCM_AAR);
164 declare!(WDT);
165 declare!(RTC1);
166 declare!(QDEC);
167 declare!(COMP_LPCOMP);
168 declare!(SWI0_EGU0);
169 declare!(SWI1_EGU1);
170 declare!(SWI2_EGU2);
171 declare!(SWI3_EGU3);
172 declare!(SWI4_EGU4);
173 declare!(SWI5_EGU5);
174 declare!(TIMER3);
175 declare!(TIMER4);
176 declare!(PWM0);
177 declare!(PDM);
178 declare!(MWU);
179 declare!(PWM1);
180 declare!(PWM2);
181 declare!(SPIM2_SPIS2_SPI2);
182 declare!(RTC2);
183 declare!(I2S);
184 declare!(FPU);
95} 185}
96 186
97#[inline] 187#[cfg(feature = "52833")]
98pub fn is_enabled(irq: Interrupt) -> bool { 188mod irqs {
99 NVIC::is_enabled(irq) 189 use super::*;
190 declare!(POWER_CLOCK);
191 declare!(RADIO);
192 declare!(UARTE0_UART0);
193 declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
194 declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
195 declare!(NFCT);
196 declare!(GPIOTE);
197 declare!(SAADC);
198 declare!(TIMER0);
199 declare!(TIMER1);
200 declare!(TIMER2);
201 declare!(RTC0);
202 declare!(TEMP);
203 declare!(RNG);
204 declare!(ECB);
205 declare!(CCM_AAR);
206 declare!(WDT);
207 declare!(RTC1);
208 declare!(QDEC);
209 declare!(COMP_LPCOMP);
210 declare!(SWI0_EGU0);
211 declare!(SWI1_EGU1);
212 declare!(SWI2_EGU2);
213 declare!(SWI3_EGU3);
214 declare!(SWI4_EGU4);
215 declare!(SWI5_EGU5);
216 declare!(TIMER3);
217 declare!(TIMER4);
218 declare!(PWM0);
219 declare!(PDM);
220 declare!(MWU);
221 declare!(PWM1);
222 declare!(PWM2);
223 declare!(SPIM2_SPIS2_SPI2);
224 declare!(RTC2);
225 declare!(I2S);
226 declare!(FPU);
227 declare!(USBD);
228 declare!(UARTE1);
229 declare!(PWM3);
230 declare!(SPIM3);
100} 231}
101 232
102#[inline] 233#[cfg(feature = "52840")]
103pub fn is_pending(irq: Interrupt) -> bool { 234mod irqs {
104 NVIC::is_pending(irq) 235 use super::*;
236 declare!(POWER_CLOCK);
237 declare!(RADIO);
238 declare!(UARTE0_UART0);
239 declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
240 declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
241 declare!(NFCT);
242 declare!(GPIOTE);
243 declare!(SAADC);
244 declare!(TIMER0);
245 declare!(TIMER1);
246 declare!(TIMER2);
247 declare!(RTC0);
248 declare!(TEMP);
249 declare!(RNG);
250 declare!(ECB);
251 declare!(CCM_AAR);
252 declare!(WDT);
253 declare!(RTC1);
254 declare!(QDEC);
255 declare!(COMP_LPCOMP);
256 declare!(SWI0_EGU0);
257 declare!(SWI1_EGU1);
258 declare!(SWI2_EGU2);
259 declare!(SWI3_EGU3);
260 declare!(SWI4_EGU4);
261 declare!(SWI5_EGU5);
262 declare!(TIMER3);
263 declare!(TIMER4);
264 declare!(PWM0);
265 declare!(PDM);
266 declare!(MWU);
267 declare!(PWM1);
268 declare!(PWM2);
269 declare!(SPIM2_SPIS2_SPI2);
270 declare!(RTC2);
271 declare!(I2S);
272 declare!(FPU);
273 declare!(USBD);
274 declare!(UARTE1);
275 declare!(QSPI);
276 declare!(CRYPTOCELL);
277 declare!(PWM3);
278 declare!(SPIM3);
105} 279}
106 280
107#[inline] 281pub use irqs::*;
108pub fn pend(irq: Interrupt) {
109 NVIC::pend(irq)
110}
111
112#[inline]
113pub fn unpend(irq: Interrupt) {
114 NVIC::unpend(irq)
115}
116
117#[inline]
118pub fn get_priority(irq: Interrupt) -> Priority {
119 Priority::from_nvic(NVIC::get_priority(irq))
120}
121
122#[inline]
123pub fn set_priority(irq: Interrupt, prio: Priority) {
124 unsafe {
125 cortex_m::peripheral::Peripherals::steal()
126 .NVIC
127 .set_priority(irq, prio.to_nvic())
128 }
129}
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