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authorRaul Alimbekov <[email protected]>2025-12-16 09:05:22 +0300
committerGitHub <[email protected]>2025-12-16 09:05:22 +0300
commitc9a04b4b732b7a3b696eb8223664c1a7942b1875 (patch)
tree6dbe5c02e66eed8d8762f13f95afd24f8db2b38c /embassy-nrf/src/spis.rs
parentcde24a3ef1117653ba5ed4184102b33f745782fb (diff)
parent5ae6e060ec1c90561719aabdc29d5b6e7b8b0a82 (diff)
Merge branch 'main' into main
Diffstat (limited to 'embassy-nrf/src/spis.rs')
-rw-r--r--embassy-nrf/src/spis.rs37
1 files changed, 26 insertions, 11 deletions
diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 713163a55..6f837c317 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -3,20 +3,21 @@
3#![macro_use] 3#![macro_use]
4use core::future::poll_fn; 4use core::future::poll_fn;
5use core::marker::PhantomData; 5use core::marker::PhantomData;
6use core::sync::atomic::{compiler_fence, Ordering}; 6use core::sync::atomic::{Ordering, compiler_fence};
7use core::task::Poll; 7use core::task::Poll;
8 8
9use embassy_embedded_hal::SetConfig; 9use embassy_embedded_hal::SetConfig;
10use embassy_hal_internal::{Peri, PeripheralType}; 10use embassy_hal_internal::{Peri, PeripheralType};
11use embassy_sync::waitqueue::AtomicWaker; 11use embassy_sync::waitqueue::AtomicWaker;
12pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; 12pub use embedded_hal_02::spi::{MODE_0, MODE_1, MODE_2, MODE_3, Mode, Phase, Polarity};
13pub use pac::spis::vals::Order as BitOrder; 13pub use pac::spis::vals::Order as BitOrder;
14 14
15use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; 15use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
16use crate::gpio::{self, convert_drive, AnyPin, OutputDrive, Pin as GpioPin, SealedPin as _}; 16use crate::gpio::{self, AnyPin, OutputDrive, Pin as GpioPin, SealedPin as _, convert_drive};
17use crate::interrupt::typelevel::Interrupt; 17use crate::interrupt::typelevel::Interrupt;
18use crate::pac::gpio::vals as gpiovals; 18use crate::pac::gpio::vals as gpiovals;
19use crate::pac::spis::vals; 19use crate::pac::spis::vals;
20use crate::ppi::Event;
20use crate::util::slice_in_ram_or; 21use crate::util::slice_in_ram_or;
21use crate::{interrupt, pac}; 22use crate::{interrupt, pac};
22 23
@@ -224,15 +225,15 @@ impl<'d> Spis<'d> {
224 if tx.len() > EASY_DMA_SIZE { 225 if tx.len() > EASY_DMA_SIZE {
225 return Err(Error::TxBufferTooLong); 226 return Err(Error::TxBufferTooLong);
226 } 227 }
227 r.txd().ptr().write_value(tx as *const u8 as _); 228 r.dma().tx().ptr().write_value(tx as *const u8 as _);
228 r.txd().maxcnt().write(|w| w.set_maxcnt(tx.len() as _)); 229 r.dma().tx().maxcnt().write(|w| w.set_maxcnt(tx.len() as _));
229 230
230 // Set up the DMA read. 231 // Set up the DMA read.
231 if rx.len() > EASY_DMA_SIZE { 232 if rx.len() > EASY_DMA_SIZE {
232 return Err(Error::RxBufferTooLong); 233 return Err(Error::RxBufferTooLong);
233 } 234 }
234 r.rxd().ptr().write_value(rx as *mut u8 as _); 235 r.dma().rx().ptr().write_value(rx as *mut u8 as _);
235 r.rxd().maxcnt().write(|w| w.set_maxcnt(rx.len() as _)); 236 r.dma().rx().maxcnt().write(|w| w.set_maxcnt(rx.len() as _));
236 237
237 // Reset end event. 238 // Reset end event.
238 r.events_end().write_value(0); 239 r.events_end().write_value(0);
@@ -260,8 +261,8 @@ impl<'d> Spis<'d> {
260 // Wait for 'end' event. 261 // Wait for 'end' event.
261 while r.events_end().read() == 0 {} 262 while r.events_end().read() == 0 {}
262 263
263 let n_rx = r.rxd().amount().read().0 as usize; 264 let n_rx = r.dma().rx().amount().read().0 as usize;
264 let n_tx = r.txd().amount().read().0 as usize; 265 let n_tx = r.dma().tx().amount().read().0 as usize;
265 266
266 compiler_fence(Ordering::SeqCst); 267 compiler_fence(Ordering::SeqCst);
267 268
@@ -326,14 +327,28 @@ impl<'d> Spis<'d> {
326 }) 327 })
327 .await; 328 .await;
328 329
329 let n_rx = r.rxd().amount().read().0 as usize; 330 let n_rx = r.dma().rx().amount().read().0 as usize;
330 let n_tx = r.txd().amount().read().0 as usize; 331 let n_tx = r.dma().tx().amount().read().0 as usize;
331 332
332 compiler_fence(Ordering::SeqCst); 333 compiler_fence(Ordering::SeqCst);
333 334
334 Ok((n_rx, n_tx)) 335 Ok((n_rx, n_tx))
335 } 336 }
336 337
338 /// Returns the ACQUIRED event, for use with PPI.
339 ///
340 /// This event will fire when the semaphore is acquired.
341 pub fn event_acquired(&self) -> Event<'d> {
342 Event::from_reg(self.r.events_acquired())
343 }
344
345 /// Returns the END event, for use with PPI.
346 ///
347 /// This event will fire when the slave transaction is complete.
348 pub fn event_end(&self) -> Event<'d> {
349 Event::from_reg(self.r.events_end())
350 }
351
337 async fn async_inner(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(usize, usize), Error> { 352 async fn async_inner(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(usize, usize), Error> {
338 match self.async_inner_from_ram(rx, tx).await { 353 match self.async_inner_from_ram(rx, tx).await {
339 Ok(n) => Ok(n), 354 Ok(n) => Ok(n),