aboutsummaryrefslogtreecommitdiff
path: root/embassy-nrf/src/uarte.rs
diff options
context:
space:
mode:
authorDario Nieuwenhuis <[email protected]>2024-02-21 22:29:37 +0100
committerDario Nieuwenhuis <[email protected]>2024-02-21 22:29:37 +0100
commit4fbe18f82134567af4766d161e8385c7dd919a0b (patch)
treec681ce44b8675ba9c5f0767fdfad632133e75f7b /embassy-nrf/src/uarte.rs
parent1f17fdf84ee30f989a1a5bd8945a76a9f5edac4b (diff)
nrf/uart: share waker state between buffered and nonbuffered.
Diffstat (limited to 'embassy-nrf/src/uarte.rs')
-rw-r--r--embassy-nrf/src/uarte.rs18
1 files changed, 9 insertions, 9 deletions
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 90820acab..cd14c718a 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -115,7 +115,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
115 let endrx = r.events_endrx.read().bits(); 115 let endrx = r.events_endrx.read().bits();
116 let error = r.events_error.read().bits(); 116 let error = r.events_error.read().bits();
117 if endrx != 0 || error != 0 { 117 if endrx != 0 || error != 0 {
118 s.endrx_waker.wake(); 118 s.rx_waker.wake();
119 if endrx != 0 { 119 if endrx != 0 {
120 r.intenclr.write(|w| w.endrx().clear()); 120 r.intenclr.write(|w| w.endrx().clear());
121 } 121 }
@@ -124,7 +124,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
124 } 124 }
125 } 125 }
126 if r.events_endtx.read().bits() != 0 { 126 if r.events_endtx.read().bits() != 0 {
127 s.endtx_waker.wake(); 127 s.tx_waker.wake();
128 r.intenclr.write(|w| w.endtx().clear()); 128 r.intenclr.write(|w| w.endtx().clear());
129 } 129 }
130 } 130 }
@@ -433,7 +433,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
433 r.tasks_starttx.write(|w| unsafe { w.bits(1) }); 433 r.tasks_starttx.write(|w| unsafe { w.bits(1) });
434 434
435 poll_fn(|cx| { 435 poll_fn(|cx| {
436 s.endtx_waker.register(cx.waker()); 436 s.tx_waker.register(cx.waker());
437 if r.events_endtx.read().bits() != 0 { 437 if r.events_endtx.read().bits() != 0 {
438 return Poll::Ready(()); 438 return Poll::Ready(());
439 } 439 }
@@ -680,7 +680,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
680 r.tasks_startrx.write(|w| unsafe { w.bits(1) }); 680 r.tasks_startrx.write(|w| unsafe { w.bits(1) });
681 681
682 let result = poll_fn(|cx| { 682 let result = poll_fn(|cx| {
683 s.endrx_waker.register(cx.waker()); 683 s.rx_waker.register(cx.waker());
684 684
685 if let Err(e) = self.check_and_clear_errors() { 685 if let Err(e) = self.check_and_clear_errors() {
686 r.tasks_stoprx.write(|w| unsafe { w.bits(1) }); 686 r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
@@ -827,7 +827,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
827 r.tasks_startrx.write(|w| unsafe { w.bits(1) }); 827 r.tasks_startrx.write(|w| unsafe { w.bits(1) });
828 828
829 let result = poll_fn(|cx| { 829 let result = poll_fn(|cx| {
830 s.endrx_waker.register(cx.waker()); 830 s.rx_waker.register(cx.waker());
831 831
832 if let Err(e) = self.rx.check_and_clear_errors() { 832 if let Err(e) = self.rx.check_and_clear_errors() {
833 r.tasks_stoprx.write(|w| unsafe { w.bits(1) }); 833 r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
@@ -970,15 +970,15 @@ pub(crate) mod sealed {
970 use super::*; 970 use super::*;
971 971
972 pub struct State { 972 pub struct State {
973 pub endrx_waker: AtomicWaker, 973 pub rx_waker: AtomicWaker,
974 pub endtx_waker: AtomicWaker, 974 pub tx_waker: AtomicWaker,
975 pub tx_rx_refcount: AtomicU8, 975 pub tx_rx_refcount: AtomicU8,
976 } 976 }
977 impl State { 977 impl State {
978 pub const fn new() -> Self { 978 pub const fn new() -> Self {
979 Self { 979 Self {
980 endrx_waker: AtomicWaker::new(), 980 rx_waker: AtomicWaker::new(),
981 endtx_waker: AtomicWaker::new(), 981 tx_waker: AtomicWaker::new(),
982 tx_rx_refcount: AtomicU8::new(0), 982 tx_rx_refcount: AtomicU8::new(0),
983 } 983 }
984 } 984 }