diff options
| author | Priit Laes <[email protected]> | 2024-02-17 13:02:56 +0200 |
|---|---|---|
| committer | Priit Laes <[email protected]> | 2024-02-17 13:30:19 +0200 |
| commit | bb2fb59a87d3aa1322cb13280287851d3ec39f59 (patch) | |
| tree | bcb2f83c9aa73d13a772cc92b2eb6e2949986e5b /embassy-nrf/src/uarte.rs | |
| parent | 1aa999c2a825bdaf6fa4c980f47428d9b1d9263f (diff) | |
nrf: Remove useless borrows
Diffstat (limited to 'embassy-nrf/src/uarte.rs')
| -rw-r--r-- | embassy-nrf/src/uarte.rs | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs index 3d486452f..67b3feae7 100644 --- a/embassy-nrf/src/uarte.rs +++ b/embassy-nrf/src/uarte.rs | |||
| @@ -308,7 +308,7 @@ fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) { | |||
| 308 | r.events_txstarted.reset(); | 308 | r.events_txstarted.reset(); |
| 309 | 309 | ||
| 310 | // Enable | 310 | // Enable |
| 311 | apply_workaround_for_enable_anomaly(&r); | 311 | apply_workaround_for_enable_anomaly(r); |
| 312 | r.enable.write(|w| w.enable().enabled()); | 312 | r.enable.write(|w| w.enable().enabled()); |
| 313 | } | 313 | } |
| 314 | 314 | ||
| @@ -378,7 +378,7 @@ impl<'d, T: Instance> UarteTx<'d, T> { | |||
| 378 | trace!("Copying UARTE tx buffer into RAM for DMA"); | 378 | trace!("Copying UARTE tx buffer into RAM for DMA"); |
| 379 | let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()]; | 379 | let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()]; |
| 380 | ram_buf.copy_from_slice(buffer); | 380 | ram_buf.copy_from_slice(buffer); |
| 381 | self.write_from_ram(&ram_buf).await | 381 | self.write_from_ram(ram_buf).await |
| 382 | } | 382 | } |
| 383 | Err(error) => Err(error), | 383 | Err(error) => Err(error), |
| 384 | } | 384 | } |
| @@ -448,7 +448,7 @@ impl<'d, T: Instance> UarteTx<'d, T> { | |||
| 448 | trace!("Copying UARTE tx buffer into RAM for DMA"); | 448 | trace!("Copying UARTE tx buffer into RAM for DMA"); |
| 449 | let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()]; | 449 | let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()]; |
| 450 | ram_buf.copy_from_slice(buffer); | 450 | ram_buf.copy_from_slice(buffer); |
| 451 | self.blocking_write_from_ram(&ram_buf) | 451 | self.blocking_write_from_ram(ram_buf) |
| 452 | } | 452 | } |
| 453 | Err(error) => Err(error), | 453 | Err(error) => Err(error), |
| 454 | } | 454 | } |
| @@ -504,7 +504,7 @@ impl<'a, T: Instance> Drop for UarteTx<'a, T> { | |||
| 504 | 504 | ||
| 505 | let s = T::state(); | 505 | let s = T::state(); |
| 506 | 506 | ||
| 507 | drop_tx_rx(&r, &s); | 507 | drop_tx_rx(r, s); |
| 508 | } | 508 | } |
| 509 | } | 509 | } |
| 510 | 510 | ||
| @@ -744,7 +744,7 @@ impl<'a, T: Instance> Drop for UarteRx<'a, T> { | |||
| 744 | 744 | ||
| 745 | let s = T::state(); | 745 | let s = T::state(); |
| 746 | 746 | ||
| 747 | drop_tx_rx(&r, &s); | 747 | drop_tx_rx(r, s); |
| 748 | } | 748 | } |
| 749 | } | 749 | } |
| 750 | 750 | ||
