diff options
| author | Dario Nieuwenhuis <[email protected]> | 2024-06-17 22:50:13 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2024-06-25 23:18:16 +0200 |
| commit | c48547b475eb039a9d30f4c1e03d0c9f65cdec18 (patch) | |
| tree | b4f389f2f13b96d9aca2f9bcd59cac26342251b8 /embassy-nrf/src/uarte.rs | |
| parent | e4c4036a46218b3ba4bde28e4e056a439ac7055b (diff) | |
nrf: fix wrong order configuring gpios.
Docs say "PSEL.RXD, PSEL.RTS, PSEL.RTS, and PSEL.TXD must only be configured when the UARTE is disabled."
For some reason nrf52 doesn't care but nrf91 does.
Diffstat (limited to 'embassy-nrf/src/uarte.rs')
| -rw-r--r-- | embassy-nrf/src/uarte.rs | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs index fa0a773a8..4cf193617 100644 --- a/embassy-nrf/src/uarte.rs +++ b/embassy-nrf/src/uarte.rs | |||
| @@ -221,6 +221,7 @@ impl<'d, T: Instance> Uarte<'d, T> { | |||
| 221 | 221 | ||
| 222 | T::Interrupt::unpend(); | 222 | T::Interrupt::unpend(); |
| 223 | unsafe { T::Interrupt::enable() }; | 223 | unsafe { T::Interrupt::enable() }; |
| 224 | r.enable.write(|w| w.enable().enabled()); | ||
| 224 | 225 | ||
| 225 | let s = T::state(); | 226 | let s = T::state(); |
| 226 | s.tx_rx_refcount.store(2, Ordering::Relaxed); | 227 | s.tx_rx_refcount.store(2, Ordering::Relaxed); |
| @@ -319,9 +320,7 @@ pub(crate) fn configure(r: &RegisterBlock, config: Config, hardware_flow_control | |||
| 319 | r.psel.cts.write(|w| w.connect().disconnected()); | 320 | r.psel.cts.write(|w| w.connect().disconnected()); |
| 320 | r.psel.rts.write(|w| w.connect().disconnected()); | 321 | r.psel.rts.write(|w| w.connect().disconnected()); |
| 321 | 322 | ||
| 322 | // Enable | ||
| 323 | apply_workaround_for_enable_anomaly(r); | 323 | apply_workaround_for_enable_anomaly(r); |
| 324 | r.enable.write(|w| w.enable().enabled()); | ||
| 325 | } | 324 | } |
| 326 | 325 | ||
| 327 | impl<'d, T: Instance> UarteTx<'d, T> { | 326 | impl<'d, T: Instance> UarteTx<'d, T> { |
| @@ -369,6 +368,7 @@ impl<'d, T: Instance> UarteTx<'d, T> { | |||
| 369 | 368 | ||
| 370 | T::Interrupt::unpend(); | 369 | T::Interrupt::unpend(); |
| 371 | unsafe { T::Interrupt::enable() }; | 370 | unsafe { T::Interrupt::enable() }; |
| 371 | r.enable.write(|w| w.enable().enabled()); | ||
| 372 | 372 | ||
| 373 | let s = T::state(); | 373 | let s = T::state(); |
| 374 | s.tx_rx_refcount.store(1, Ordering::Relaxed); | 374 | s.tx_rx_refcount.store(1, Ordering::Relaxed); |
| @@ -567,6 +567,7 @@ impl<'d, T: Instance> UarteRx<'d, T> { | |||
| 567 | 567 | ||
| 568 | T::Interrupt::unpend(); | 568 | T::Interrupt::unpend(); |
| 569 | unsafe { T::Interrupt::enable() }; | 569 | unsafe { T::Interrupt::enable() }; |
| 570 | r.enable.write(|w| w.enable().enabled()); | ||
| 570 | 571 | ||
| 571 | let s = T::state(); | 572 | let s = T::state(); |
| 572 | s.tx_rx_refcount.store(1, Ordering::Relaxed); | 573 | s.tx_rx_refcount.store(1, Ordering::Relaxed); |
