diff options
| author | Justin Beaurivage <[email protected]> | 2024-01-31 14:16:58 -0500 |
|---|---|---|
| committer | Justin Beaurivage <[email protected]> | 2024-01-31 14:16:58 -0500 |
| commit | d364447a34377c708fe6a7ea87aabda3ea1231ba (patch) | |
| tree | b42040adec5a6a8f93d4262477deea56fc68edb0 /embassy-nrf/src/uarte.rs | |
| parent | 7ff21e8b8ba3bd03b4317abbc40f0e6a0b02289f (diff) | |
Add error handling to UarteRxWithIdle
Diffstat (limited to 'embassy-nrf/src/uarte.rs')
| -rw-r--r-- | embassy-nrf/src/uarte.rs | 35 |
1 files changed, 23 insertions, 12 deletions
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs index 90d851139..97c887ab2 100644 --- a/embassy-nrf/src/uarte.rs +++ b/embassy-nrf/src/uarte.rs | |||
| @@ -534,7 +534,8 @@ impl<'d, T: Instance> UarteRx<'d, T> { | |||
| 534 | Self::new_inner(uarte, rxd.map_into(), Some(rts.map_into()), config) | 534 | Self::new_inner(uarte, rxd.map_into(), Some(rts.map_into()), config) |
| 535 | } | 535 | } |
| 536 | 536 | ||
| 537 | fn read_and_clear_errors(&mut self) -> Result<(), Error> { | 537 | /// Check for errors and clear the error register if an error occured. |
| 538 | fn check_and_clear_errors(&mut self) -> Result<(), Error> { | ||
| 538 | let r = T::regs(); | 539 | let r = T::regs(); |
| 539 | let err_bits = r.errorsrc.read().bits(); | 540 | let err_bits = r.errorsrc.read().bits(); |
| 540 | r.errorsrc.write(|w| unsafe { w.bits(err_bits) }); | 541 | r.errorsrc.write(|w| unsafe { w.bits(err_bits) }); |
| @@ -675,8 +676,7 @@ impl<'d, T: Instance> UarteRx<'d, T> { | |||
| 675 | let result = poll_fn(|cx| { | 676 | let result = poll_fn(|cx| { |
| 676 | s.endrx_waker.register(cx.waker()); | 677 | s.endrx_waker.register(cx.waker()); |
| 677 | 678 | ||
| 678 | let maybe_err = self.read_and_clear_errors(); | 679 | if let Err(e) = self.check_and_clear_errors() { |
| 679 | if let Err(e) = maybe_err { | ||
| 680 | return Poll::Ready(Err(e)); | 680 | return Poll::Ready(Err(e)); |
| 681 | } | 681 | } |
| 682 | if r.events_endrx.read().bits() != 0 { | 682 | if r.events_endrx.read().bits() != 0 { |
| @@ -727,7 +727,7 @@ impl<'d, T: Instance> UarteRx<'d, T> { | |||
| 727 | compiler_fence(Ordering::SeqCst); | 727 | compiler_fence(Ordering::SeqCst); |
| 728 | r.events_rxstarted.reset(); | 728 | r.events_rxstarted.reset(); |
| 729 | 729 | ||
| 730 | self.read_and_clear_errors() | 730 | self.check_and_clear_errors() |
| 731 | } | 731 | } |
| 732 | } | 732 | } |
| 733 | 733 | ||
| @@ -794,8 +794,12 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> { | |||
| 794 | let drop = OnDrop::new(|| { | 794 | let drop = OnDrop::new(|| { |
| 795 | self.timer.stop(); | 795 | self.timer.stop(); |
| 796 | 796 | ||
| 797 | r.intenclr.write(|w| w.endrx().clear()); | 797 | r.intenclr.write(|w| { |
| 798 | w.endrx().clear(); | ||
| 799 | w.error().clear() | ||
| 800 | }); | ||
| 798 | r.events_rxto.reset(); | 801 | r.events_rxto.reset(); |
| 802 | r.events_error.reset(); | ||
| 799 | r.tasks_stoprx.write(|w| unsafe { w.bits(1) }); | 803 | r.tasks_stoprx.write(|w| unsafe { w.bits(1) }); |
| 800 | 804 | ||
| 801 | while r.events_endrx.read().bits() == 0 {} | 805 | while r.events_endrx.read().bits() == 0 {} |
| @@ -805,17 +809,23 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> { | |||
| 805 | r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) }); | 809 | r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) }); |
| 806 | 810 | ||
| 807 | r.events_endrx.reset(); | 811 | r.events_endrx.reset(); |
| 808 | r.intenset.write(|w| w.endrx().set()); | 812 | r.events_error.reset(); |
| 813 | r.intenset.write(|w| {w.endrx().set(); w.error().set()}); | ||
| 809 | 814 | ||
| 810 | compiler_fence(Ordering::SeqCst); | 815 | compiler_fence(Ordering::SeqCst); |
| 811 | 816 | ||
| 812 | r.tasks_startrx.write(|w| unsafe { w.bits(1) }); | 817 | r.tasks_startrx.write(|w| unsafe { w.bits(1) }); |
| 813 | 818 | ||
| 814 | poll_fn(|cx| { | 819 | let result = poll_fn(|cx| { |
| 815 | s.endrx_waker.register(cx.waker()); | 820 | s.endrx_waker.register(cx.waker()); |
| 821 | |||
| 822 | if let Err(e) = self.rx.check_and_clear_errors() { | ||
| 823 | return Poll::Ready(Err(e)); | ||
| 824 | } | ||
| 816 | if r.events_endrx.read().bits() != 0 { | 825 | if r.events_endrx.read().bits() != 0 { |
| 817 | return Poll::Ready(()); | 826 | return Poll::Ready(Ok(())); |
| 818 | } | 827 | } |
| 828 | |||
| 819 | Poll::Pending | 829 | Poll::Pending |
| 820 | }) | 830 | }) |
| 821 | .await; | 831 | .await; |
| @@ -828,7 +838,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> { | |||
| 828 | 838 | ||
| 829 | drop.defuse(); | 839 | drop.defuse(); |
| 830 | 840 | ||
| 831 | Ok(n) | 841 | result.map(|_| n) |
| 832 | } | 842 | } |
| 833 | 843 | ||
| 834 | /// Read bytes until the buffer is filled, or the line becomes idle. | 844 | /// Read bytes until the buffer is filled, or the line becomes idle. |
| @@ -853,13 +863,14 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> { | |||
| 853 | r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) }); | 863 | r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) }); |
| 854 | 864 | ||
| 855 | r.events_endrx.reset(); | 865 | r.events_endrx.reset(); |
| 856 | r.intenclr.write(|w| w.endrx().clear()); | 866 | r.events_error.reset(); |
| 867 | r.intenclr.write(|w| {w.endrx().clear(); w.error().clear()}); | ||
| 857 | 868 | ||
| 858 | compiler_fence(Ordering::SeqCst); | 869 | compiler_fence(Ordering::SeqCst); |
| 859 | 870 | ||
| 860 | r.tasks_startrx.write(|w| unsafe { w.bits(1) }); | 871 | r.tasks_startrx.write(|w| unsafe { w.bits(1) }); |
| 861 | 872 | ||
| 862 | while r.events_endrx.read().bits() == 0 {} | 873 | while r.events_endrx.read().bits() == 0 && r.events_error.read().bits() == 0 {} |
| 863 | 874 | ||
| 864 | compiler_fence(Ordering::SeqCst); | 875 | compiler_fence(Ordering::SeqCst); |
| 865 | let n = r.rxd.amount.read().amount().bits() as usize; | 876 | let n = r.rxd.amount.read().amount().bits() as usize; |
| @@ -867,7 +878,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> { | |||
| 867 | self.timer.stop(); | 878 | self.timer.stop(); |
| 868 | r.events_rxstarted.reset(); | 879 | r.events_rxstarted.reset(); |
| 869 | 880 | ||
| 870 | Ok(n) | 881 | self.rx.check_and_clear_errors().map(|_| n) |
| 871 | } | 882 | } |
| 872 | } | 883 | } |
| 873 | 884 | ||
