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authorArdelean Calin <[email protected]>2022-11-22 17:35:38 +0200
committerArdelean Calin <[email protected]>2022-11-22 17:35:38 +0200
commit64c2e1b9b670fda7446a0df6eeb2db5dce2aa1c2 (patch)
treecbdd0a2c2a3b28a0bb763bc7a4bcade83e6ef41f /embassy-nrf/src
parenta074cd0625d68e72694c6575063ae53a840d12dc (diff)
Switched to PeripheralRef for channel.
Diffstat (limited to 'embassy-nrf/src')
-rw-r--r--embassy-nrf/src/gpiote.rs43
1 files changed, 20 insertions, 23 deletions
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 4f11f33ef..6fac2c371 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -2,7 +2,7 @@ use core::convert::Infallible;
2use core::future::{poll_fn, Future}; 2use core::future::{poll_fn, Future};
3use core::task::{Context, Poll}; 3use core::task::{Context, Poll};
4 4
5use embassy_hal_common::{impl_peripheral, Peripheral, PeripheralRef}; 5use embassy_hal_common::{impl_peripheral, Peripheral, PeripheralRef, into_ref};
6use embassy_sync::waitqueue::AtomicWaker; 6use embassy_sync::waitqueue::AtomicWaker;
7 7
8use crate::gpio::sealed::Pin as _; 8use crate::gpio::sealed::Pin as _;
@@ -148,21 +148,23 @@ impl Iterator for BitIter {
148 148
149/// GPIOTE channel driver in input mode 149/// GPIOTE channel driver in input mode
150pub struct InputChannel<'d, C: Channel, T: GpioPin> { 150pub struct InputChannel<'d, C: Channel, T: GpioPin> {
151 ch: C, 151 _ch: PeripheralRef<'d, C>,
152 pin: Input<'d, T>, 152 pin: Input<'d, T>,
153} 153}
154 154
155impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> { 155impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> {
156 fn drop(&mut self) { 156 fn drop(&mut self) {
157 let g = regs(); 157 let g = regs();
158 let num = self.ch.number(); 158 let num = self._ch.number();
159 g.config[num].write(|w| w.mode().disabled()); 159 g.config[num].write(|w| w.mode().disabled());
160 g.intenclr.write(|w| unsafe { w.bits(1 << num) }); 160 g.intenclr.write(|w| unsafe { w.bits(1 << num) });
161 } 161 }
162} 162}
163 163
164impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> { 164impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
165 pub fn new(ch: C, pin: Input<'d, T>, polarity: InputChannelPolarity) -> Self { 165 pub fn new(ch: impl Peripheral<P = C> + 'd, pin: Input<'d, T>, polarity: InputChannelPolarity) -> Self {
166 into_ref!(ch);
167
166 let g = regs(); 168 let g = regs();
167 let num = ch.number(); 169 let num = ch.number();
168 170
@@ -183,12 +185,12 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
183 185
184 g.events_in[num].reset(); 186 g.events_in[num].reset();
185 187
186 InputChannel { ch, pin } 188 InputChannel { _ch: ch, pin }
187 } 189 }
188 190
189 pub async fn wait(&self) { 191 pub async fn wait(&self) {
190 let g = regs(); 192 let g = regs();
191 let num = self.ch.number(); 193 let num = self._ch.number();
192 194
193 // Enable interrupt 195 // Enable interrupt
194 g.events_in[num].reset(); 196 g.events_in[num].reset();
@@ -209,27 +211,28 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
209 /// Returns the IN event, for use with PPI. 211 /// Returns the IN event, for use with PPI.
210 pub fn event_in(&self) -> Event { 212 pub fn event_in(&self) -> Event {
211 let g = regs(); 213 let g = regs();
212 Event::from_reg(&g.events_in[self.ch.number()]) 214 Event::from_reg(&g.events_in[self._ch.number()])
213 } 215 }
214} 216}
215 217
216/// GPIOTE channel driver in output mode 218/// GPIOTE channel driver in output mode
217pub struct OutputChannel<'d, C: Channel, T: GpioPin> { 219pub struct OutputChannel<'d, C: Channel, T: GpioPin> {
218 ch: C, 220 _ch: PeripheralRef<'d, C>,
219 _pin: Output<'d, T>, 221 _pin: Output<'d, T>,
220} 222}
221 223
222impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> { 224impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> {
223 fn drop(&mut self) { 225 fn drop(&mut self) {
224 let g = regs(); 226 let g = regs();
225 let num = self.ch.number(); 227 let num = self._ch.number();
226 g.config[num].write(|w| w.mode().disabled()); 228 g.config[num].write(|w| w.mode().disabled());
227 g.intenclr.write(|w| unsafe { w.bits(1 << num) }); 229 g.intenclr.write(|w| unsafe { w.bits(1 << num) });
228 } 230 }
229} 231}
230 232
231impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> { 233impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
232 pub fn new(ch: C, pin: Output<'d, T>, polarity: OutputChannelPolarity) -> Self { 234 pub fn new(ch: impl Peripheral<P = C> + 'd, pin: Output<'d, T>, polarity: OutputChannelPolarity) -> Self {
235 into_ref!(ch);
233 let g = regs(); 236 let g = regs();
234 let num = ch.number(); 237 let num = ch.number();
235 238
@@ -252,47 +255,47 @@ impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
252 unsafe { w.psel().bits(pin.pin.pin.pin()) } 255 unsafe { w.psel().bits(pin.pin.pin.pin()) }
253 }); 256 });
254 257
255 OutputChannel { ch, _pin: pin } 258 OutputChannel { _ch: ch, _pin: pin }
256 } 259 }
257 260
258 /// Triggers `task out` (as configured with task_out_polarity, defaults to Toggle). 261 /// Triggers `task out` (as configured with task_out_polarity, defaults to Toggle).
259 pub fn out(&self) { 262 pub fn out(&self) {
260 let g = regs(); 263 let g = regs();
261 g.tasks_out[self.ch.number()].write(|w| unsafe { w.bits(1) }); 264 g.tasks_out[self._ch.number()].write(|w| unsafe { w.bits(1) });
262 } 265 }
263 266
264 /// Triggers `task set` (set associated pin high). 267 /// Triggers `task set` (set associated pin high).
265 #[cfg(not(feature = "nrf51"))] 268 #[cfg(not(feature = "nrf51"))]
266 pub fn set(&self) { 269 pub fn set(&self) {
267 let g = regs(); 270 let g = regs();
268 g.tasks_set[self.ch.number()].write(|w| unsafe { w.bits(1) }); 271 g.tasks_set[self._ch.number()].write(|w| unsafe { w.bits(1) });
269 } 272 }
270 273
271 /// Triggers `task clear` (set associated pin low). 274 /// Triggers `task clear` (set associated pin low).
272 #[cfg(not(feature = "nrf51"))] 275 #[cfg(not(feature = "nrf51"))]
273 pub fn clear(&self) { 276 pub fn clear(&self) {
274 let g = regs(); 277 let g = regs();
275 g.tasks_clr[self.ch.number()].write(|w| unsafe { w.bits(1) }); 278 g.tasks_clr[self._ch.number()].write(|w| unsafe { w.bits(1) });
276 } 279 }
277 280
278 /// Returns the OUT task, for use with PPI. 281 /// Returns the OUT task, for use with PPI.
279 pub fn task_out(&self) -> Task { 282 pub fn task_out(&self) -> Task {
280 let g = regs(); 283 let g = regs();
281 Task::from_reg(&g.tasks_out[self.ch.number()]) 284 Task::from_reg(&g.tasks_out[self._ch.number()])
282 } 285 }
283 286
284 /// Returns the CLR task, for use with PPI. 287 /// Returns the CLR task, for use with PPI.
285 #[cfg(not(feature = "nrf51"))] 288 #[cfg(not(feature = "nrf51"))]
286 pub fn task_clr(&self) -> Task { 289 pub fn task_clr(&self) -> Task {
287 let g = regs(); 290 let g = regs();
288 Task::from_reg(&g.tasks_clr[self.ch.number()]) 291 Task::from_reg(&g.tasks_clr[self._ch.number()])
289 } 292 }
290 293
291 /// Returns the SET task, for use with PPI. 294 /// Returns the SET task, for use with PPI.
292 #[cfg(not(feature = "nrf51"))] 295 #[cfg(not(feature = "nrf51"))]
293 pub fn task_set(&self) -> Task { 296 pub fn task_set(&self) -> Task {
294 let g = regs(); 297 let g = regs();
295 Task::from_reg(&g.tasks_set[self.ch.number()]) 298 Task::from_reg(&g.tasks_set[self._ch.number()])
296 } 299 }
297} 300}
298 301
@@ -419,12 +422,6 @@ macro_rules! impl_channel {
419 $number as usize 422 $number as usize
420 } 423 }
421 } 424 }
422 impl sealed::Channel for &mut peripherals::$type {}
423 impl Channel for &mut peripherals::$type {
424 fn number(&self) -> usize {
425 $number as usize
426 }
427 }
428 }; 425 };
429} 426}
430 427