diff options
| author | Priit Laes <[email protected]> | 2023-09-06 16:44:02 +0300 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-09-10 23:17:30 +0200 |
| commit | 8413a89752b672cf21a7cd4e07a9d0f3cccfac33 (patch) | |
| tree | 4ebe5870c66a18d79cdfab557d4c665890dfcb3f /embassy-nrf/src | |
| parent | db717d9c81c76709ea84727a31fc4a201e947014 (diff) | |
nrf: spim: Use SetConfig trait internally to reduce duplication
Diffstat (limited to 'embassy-nrf/src')
| -rw-r--r-- | embassy-nrf/src/spim.rs | 40 |
1 files changed, 4 insertions, 36 deletions
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs index a468bc302..99a195a6e 100644 --- a/embassy-nrf/src/spim.rs +++ b/embassy-nrf/src/spim.rs | |||
| @@ -189,42 +189,10 @@ impl<'d, T: Instance> Spim<'d, T> { | |||
| 189 | // Enable SPIM instance. | 189 | // Enable SPIM instance. |
| 190 | r.enable.write(|w| w.enable().enabled()); | 190 | r.enable.write(|w| w.enable().enabled()); |
| 191 | 191 | ||
| 192 | // Configure mode. | 192 | let mut spim = Self { _p: spim }; |
| 193 | let mode = config.mode; | ||
| 194 | r.config.write(|w| { | ||
| 195 | match mode { | ||
| 196 | MODE_0 => { | ||
| 197 | w.order().msb_first(); | ||
| 198 | w.cpol().active_high(); | ||
| 199 | w.cpha().leading(); | ||
| 200 | } | ||
| 201 | MODE_1 => { | ||
| 202 | w.order().msb_first(); | ||
| 203 | w.cpol().active_high(); | ||
| 204 | w.cpha().trailing(); | ||
| 205 | } | ||
| 206 | MODE_2 => { | ||
| 207 | w.order().msb_first(); | ||
| 208 | w.cpol().active_low(); | ||
| 209 | w.cpha().leading(); | ||
| 210 | } | ||
| 211 | MODE_3 => { | ||
| 212 | w.order().msb_first(); | ||
| 213 | w.cpol().active_low(); | ||
| 214 | w.cpha().trailing(); | ||
| 215 | } | ||
| 216 | } | ||
| 217 | 193 | ||
| 218 | w | 194 | // Apply runtime peripheral configuration |
| 219 | }); | 195 | Self::set_config(&mut spim, &config); |
| 220 | |||
| 221 | // Configure frequency. | ||
| 222 | let frequency = config.frequency; | ||
| 223 | r.frequency.write(|w| w.frequency().variant(frequency)); | ||
| 224 | |||
| 225 | // Set over-read character | ||
| 226 | let orc = config.orc; | ||
| 227 | r.orc.write(|w| unsafe { w.orc().bits(orc) }); | ||
| 228 | 196 | ||
| 229 | // Disable all events interrupts | 197 | // Disable all events interrupts |
| 230 | r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); | 198 | r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); |
| @@ -232,7 +200,7 @@ impl<'d, T: Instance> Spim<'d, T> { | |||
| 232 | T::Interrupt::unpend(); | 200 | T::Interrupt::unpend(); |
| 233 | unsafe { T::Interrupt::enable() }; | 201 | unsafe { T::Interrupt::enable() }; |
| 234 | 202 | ||
| 235 | Self { _p: spim } | 203 | spim |
| 236 | } | 204 | } |
| 237 | 205 | ||
| 238 | fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> { | 206 | fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> { |
