Merge branch 'embassy-rs:main' into fix/simple-pwm-32bit-timer-support

35 files changed, 1088 insertions, 884 deletions

diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 29e126903..4c946497d 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -9,26 +9,27 @@
 //! Please also see [crate::uarte] to understand when [BufferedUarte] should be used.
 
 use core::cmp::min;
-use core::future::{poll_fn, Future};
+use core::future::{Future, poll_fn};
 use core::marker::PhantomData;
 use core::slice;
-use core::sync::atomic::{compiler_fence, AtomicBool, AtomicU8, AtomicUsize, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, AtomicUsize, Ordering, compiler_fence};
 use core::task::Poll;
 
-use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
 use embassy_hal_internal::Peri;
+use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
 use pac::uarte::vals;
 // Re-export SVD variants to allow user to directly set values
 pub use pac::uarte::vals::{Baudrate, ConfigParity as Parity};
 
 use crate::gpio::{AnyPin, Pin as GpioPin};
+use crate::interrupt::InterruptExt;
 use crate::interrupt::typelevel::Interrupt;
 use crate::ppi::{
     self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
 };
 use crate::timer::{Instance as TimerInstance, Timer};
-use crate::uarte::{configure, configure_rx_pins, configure_tx_pins, drop_tx_rx, Config, Instance as UarteInstance};
-use crate::{interrupt, pac, EASY_DMA_SIZE};
+use crate::uarte::{Config, Instance as UarteInstance, configure, configure_rx_pins, configure_tx_pins, drop_tx_rx};
+use crate::{EASY_DMA_SIZE, interrupt, pac};
 
 pub(crate) struct State {
     tx_buf: RingBuffer,
@@ -207,21 +208,21 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
 }
 
 /// Buffered UARTE driver.
-pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
-    tx: BufferedUarteTx<'d, U>,
-    rx: BufferedUarteRx<'d, U, T>,
+pub struct BufferedUarte<'d> {
+    tx: BufferedUarteTx<'d>,
+    rx: BufferedUarteRx<'d>,
 }
 
-impl<'d, U: UarteInstance, T: TimerInstance> Unpin for BufferedUarte<'d, U, T> {}
+impl<'d> Unpin for BufferedUarte<'d> {}
 
-impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
+impl<'d> BufferedUarte<'d> {
     /// Create a new BufferedUarte without hardware flow control.
     ///
     /// # Panics
     ///
     /// Panics if `rx_buffer.len()` is odd.
     #[allow(clippy::too_many_arguments)]
-    pub fn new(
+    pub fn new<U: UarteInstance, T: TimerInstance>(
         uarte: Peri<'d, U>,
         timer: Peri<'d, T>,
         ppi_ch1: Peri<'d, impl ConfigurableChannel>,
@@ -256,7 +257,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
     ///
     /// Panics if `rx_buffer.len()` is odd.
     #[allow(clippy::too_many_arguments)]
-    pub fn new_with_rtscts(
+    pub fn new_with_rtscts<U: UarteInstance, T: TimerInstance>(
         uarte: Peri<'d, U>,
         timer: Peri<'d, T>,
         ppi_ch1: Peri<'d, impl ConfigurableChannel>,
@@ -288,7 +289,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
     }
 
     #[allow(clippy::too_many_arguments)]
-    fn new_inner(
+    fn new_inner<U: UarteInstance, T: TimerInstance>(
         peri: Peri<'d, U>,
         timer: Peri<'d, T>,
         ppi_ch1: Peri<'d, AnyConfigurableChannel>,
@@ -302,30 +303,33 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         rx_buffer: &'d mut [u8],
         tx_buffer: &'d mut [u8],
     ) -> Self {
-        configure(U::regs(), config, cts.is_some());
+        let r = U::regs();
+        let irq = U::Interrupt::IRQ;
+        let state = U::state();
+
+        configure(r, config, cts.is_some());
 
         let tx = BufferedUarteTx::new_innerer(unsafe { peri.clone_unchecked() }, txd, cts, tx_buffer);
         let rx = BufferedUarteRx::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
 
-        U::regs().enable().write(|w| w.set_enable(vals::Enable::ENABLED));
-        U::Interrupt::pend();
-        unsafe { U::Interrupt::enable() };
+        r.enable().write(|w| w.set_enable(vals::Enable::ENABLED));
+        irq.pend();
+        unsafe { irq.enable() };
 
-        U::state().tx_rx_refcount.store(2, Ordering::Relaxed);
+        state.tx_rx_refcount.store(2, Ordering::Relaxed);
 
         Self { tx, rx }
     }
 
     /// Adjust the baud rate to the provided value.
     pub fn set_baudrate(&mut self, baudrate: Baudrate) {
-        let r = U::regs();
-        r.baudrate().write(|w| w.set_baudrate(baudrate));
+        self.tx.set_baudrate(baudrate);
     }
 
     /// Split the UART in reader and writer parts.
     ///
     /// This allows reading and writing concurrently from independent tasks.
-    pub fn split(self) -> (BufferedUarteRx<'d, U, T>, BufferedUarteTx<'d, U>) {
+    pub fn split(self) -> (BufferedUarteRx<'d>, BufferedUarteTx<'d>) {
         (self.rx, self.tx)
     }
 
@@ -333,7 +337,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
     ///
     /// The returned halves borrow from `self`, so you can drop them and go back to using
     /// the "un-split" `self`. This allows temporarily splitting the UART.
-    pub fn split_by_ref(&mut self) -> (&mut BufferedUarteRx<'d, U, T>, &mut BufferedUarteTx<'d, U>) {
+    pub fn split_by_ref(&mut self) -> (&mut BufferedUarteRx<'d>, &mut BufferedUarteTx<'d>) {
         (&mut self.rx, &mut self.tx)
     }
 
@@ -369,13 +373,17 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
 }
 
 /// Reader part of the buffered UARTE driver.
-pub struct BufferedUarteTx<'d, U: UarteInstance> {
-    _peri: Peri<'d, U>,
+pub struct BufferedUarteTx<'d> {
+    r: pac::uarte::Uarte,
+    _irq: interrupt::Interrupt,
+    state: &'static crate::uarte::State,
+    buffered_state: &'static State,
+    _p: PhantomData<&'d ()>,
 }
 
-impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
+impl<'d> BufferedUarteTx<'d> {
     /// Create a new BufferedUarteTx without hardware flow control.
-    pub fn new(
+    pub fn new<U: UarteInstance>(
         uarte: Peri<'d, U>,
         txd: Peri<'d, impl GpioPin>,
         _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
@@ -390,7 +398,7 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
     /// # Panics
     ///
     /// Panics if `rx_buffer.len()` is odd.
-    pub fn new_with_cts(
+    pub fn new_with_cts<U: UarteInstance>(
         uarte: Peri<'d, U>,
         txd: Peri<'d, impl GpioPin>,
         cts: Peri<'d, impl GpioPin>,
@@ -401,41 +409,48 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
         Self::new_inner(uarte, txd.into(), Some(cts.into()), config, tx_buffer)
     }
 
-    fn new_inner(
+    fn new_inner<U: UarteInstance>(
         peri: Peri<'d, U>,
         txd: Peri<'d, AnyPin>,
         cts: Option<Peri<'d, AnyPin>>,
         config: Config,
         tx_buffer: &'d mut [u8],
     ) -> Self {
-        configure(U::regs(), config, cts.is_some());
+        let r = U::regs();
+        let irq = U::Interrupt::IRQ;
+        let state = U::state();
+        let _buffered_state = U::buffered_state();
+
+        configure(r, config, cts.is_some());
 
         let this = Self::new_innerer(peri, txd, cts, tx_buffer);
 
-        U::regs().enable().write(|w| w.set_enable(vals::Enable::ENABLED));
-        U::Interrupt::pend();
-        unsafe { U::Interrupt::enable() };
+        r.enable().write(|w| w.set_enable(vals::Enable::ENABLED));
+        irq.pend();
+        unsafe { irq.enable() };
 
-        U::state().tx_rx_refcount.store(1, Ordering::Relaxed);
+        state.tx_rx_refcount.store(1, Ordering::Relaxed);
 
         this
     }
 
-    fn new_innerer(
-        peri: Peri<'d, U>,
+    fn new_innerer<U: UarteInstance>(
+        _peri: Peri<'d, U>,
         txd: Peri<'d, AnyPin>,
         cts: Option<Peri<'d, AnyPin>>,
         tx_buffer: &'d mut [u8],
     ) -> Self {
         let r = U::regs();
+        let irq = U::Interrupt::IRQ;
+        let state = U::state();
+        let buffered_state = U::buffered_state();
 
         configure_tx_pins(r, txd, cts);
 
         // Initialize state
-        let s = U::buffered_state();
-        s.tx_count.store(0, Ordering::Relaxed);
+        buffered_state.tx_count.store(0, Ordering::Relaxed);
         let len = tx_buffer.len();
-        unsafe { s.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
+        unsafe { buffered_state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
 
         r.events_txstarted().write_value(0);
 
@@ -444,15 +459,21 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
             w.set_endtx(true);
         });
 
-        Self { _peri: peri }
+        Self {
+            r,
+            _irq: irq,
+            state,
+            buffered_state,
+            _p: PhantomData,
+        }
     }
 
     /// Write a buffer into this writer, returning how many bytes were written.
-    pub fn write<'a>(&'a mut self, buf: &'a [u8]) -> impl Future<Output = Result<usize, Error>> + 'a {
+    pub fn write<'a>(&'a mut self, buf: &'a [u8]) -> impl Future<Output = Result<usize, Error>> + 'a + use<'a, 'd> {
         poll_fn(move |cx| {
             //trace!("poll_write: {:?}", buf.len());
-            let ss = U::state();
-            let s = U::buffered_state();
+            let ss = self.state;
+            let s = self.buffered_state;
             let mut tx = unsafe { s.tx_buf.writer() };
 
             let tx_buf = tx.push_slice();
@@ -469,7 +490,7 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
             //trace!("poll_write: queued {:?}", n);
 
             compiler_fence(Ordering::SeqCst);
-            U::Interrupt::pend();
+            self._irq.pend();
 
             Poll::Ready(Ok(n))
         })
@@ -478,7 +499,7 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
     /// Try writing a buffer without waiting, returning how many bytes were written.
     pub fn try_write(&mut self, buf: &[u8]) -> Result<usize, Error> {
         //trace!("poll_write: {:?}", buf.len());
-        let s = U::buffered_state();
+        let s = self.buffered_state;
         let mut tx = unsafe { s.tx_buf.writer() };
 
         let tx_buf = tx.push_slice();
@@ -493,17 +514,17 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
         //trace!("poll_write: queued {:?}", n);
 
         compiler_fence(Ordering::SeqCst);
-        U::Interrupt::pend();
+        self._irq.pend();
 
         Ok(n)
     }
 
     /// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
     pub fn flush(&mut self) -> impl Future<Output = Result<(), Error>> + '_ {
+        let ss = self.state;
+        let s = self.buffered_state;
         poll_fn(move |cx| {
             //trace!("poll_flush");
-            let ss = U::state();
-            let s = U::buffered_state();
             if !s.tx_buf.is_empty() {
                 //trace!("poll_flush: pending");
                 ss.tx_waker.register(cx.waker());
@@ -513,11 +534,16 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
             Poll::Ready(Ok(()))
         })
     }
+
+    /// Adjust the baud rate to the provided value.
+    pub fn set_baudrate(&mut self, baudrate: Baudrate) {
+        self.r.baudrate().write(|w| w.set_baudrate(baudrate));
+    }
 }
 
-impl<'a, U: UarteInstance> Drop for BufferedUarteTx<'a, U> {
+impl<'a> Drop for BufferedUarteTx<'a> {
     fn drop(&mut self) {
-        let r = U::regs();
+        let r = self.r;
 
         r.intenclr().write(|w| {
             w.set_txdrdy(true);
@@ -528,31 +554,34 @@ impl<'a, U: UarteInstance> Drop for BufferedUarteTx<'a, U> {
         r.tasks_stoptx().write_value(1);
         while r.events_txstopped().read() == 0 {}
 
-        let s = U::buffered_state();
+        let s = self.buffered_state;
         unsafe { s.tx_buf.deinit() }
 
-        let s = U::state();
+        let s = self.state;
         drop_tx_rx(r, s);
     }
 }
 
 /// Reader part of the buffered UARTE driver.
-pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> {
-    _peri: Peri<'d, U>,
-    timer: Timer<'d, T>,
+pub struct BufferedUarteRx<'d> {
+    r: pac::uarte::Uarte,
+    state: &'static crate::uarte::State,
+    buffered_state: &'static State,
+    timer: Timer<'d>,
     _ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>,
     _ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>,
     _ppi_group: PpiGroup<'d, AnyGroup>,
+    _p: PhantomData<&'d ()>,
 }
 
-impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
+impl<'d> BufferedUarteRx<'d> {
     /// Create a new BufferedUarte without hardware flow control.
     ///
     /// # Panics
     ///
     /// Panics if `rx_buffer.len()` is odd.
     #[allow(clippy::too_many_arguments)]
-    pub fn new(
+    pub fn new<U: UarteInstance, T: TimerInstance>(
         uarte: Peri<'d, U>,
         timer: Peri<'d, T>,
         ppi_ch1: Peri<'d, impl ConfigurableChannel>,
@@ -582,7 +611,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
     ///
     /// Panics if `rx_buffer.len()` is odd.
     #[allow(clippy::too_many_arguments)]
-    pub fn new_with_rts(
+    pub fn new_with_rts<U: UarteInstance, T: TimerInstance>(
         uarte: Peri<'d, U>,
         timer: Peri<'d, T>,
         ppi_ch1: Peri<'d, impl ConfigurableChannel>,
@@ -608,7 +637,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
     }
 
     #[allow(clippy::too_many_arguments)]
-    fn new_inner(
+    fn new_inner<U: UarteInstance, T: TimerInstance>(
         peri: Peri<'d, U>,
         timer: Peri<'d, T>,
         ppi_ch1: Peri<'d, AnyConfigurableChannel>,
@@ -619,22 +648,27 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
         config: Config,
         rx_buffer: &'d mut [u8],
     ) -> Self {
-        configure(U::regs(), config, rts.is_some());
+        let r = U::regs();
+        let irq = U::Interrupt::IRQ;
+        let state = U::state();
+        let _buffered_state = U::buffered_state();
+
+        configure(r, config, rts.is_some());
 
         let this = Self::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
 
-        U::regs().enable().write(|w| w.set_enable(vals::Enable::ENABLED));
-        U::Interrupt::pend();
-        unsafe { U::Interrupt::enable() };
+        r.enable().write(|w| w.set_enable(vals::Enable::ENABLED));
+        irq.pend();
+        unsafe { irq.enable() };
 
-        U::state().tx_rx_refcount.store(1, Ordering::Relaxed);
+        state.tx_rx_refcount.store(1, Ordering::Relaxed);
 
         this
     }
 
     #[allow(clippy::too_many_arguments)]
-    fn new_innerer(
-        peri: Peri<'d, U>,
+    fn new_innerer<U: UarteInstance, T: TimerInstance>(
+        _peri: Peri<'d, U>,
         timer: Peri<'d, T>,
         ppi_ch1: Peri<'d, AnyConfigurableChannel>,
         ppi_ch2: Peri<'d, AnyConfigurableChannel>,
@@ -646,16 +680,17 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
         assert!(rx_buffer.len() % 2 == 0);
 
         let r = U::regs();
+        let state = U::state();
+        let buffered_state = U::buffered_state();
 
         configure_rx_pins(r, rxd, rts);
 
         // Initialize state
-        let s = U::buffered_state();
-        s.rx_started_count.store(0, Ordering::Relaxed);
-        s.rx_ended_count.store(0, Ordering::Relaxed);
-        s.rx_started.store(false, Ordering::Relaxed);
+        buffered_state.rx_started_count.store(0, Ordering::Relaxed);
+        buffered_state.rx_ended_count.store(0, Ordering::Relaxed);
+        buffered_state.rx_started.store(false, Ordering::Relaxed);
         let rx_len = rx_buffer.len().min(EASY_DMA_SIZE * 2);
-        unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), rx_len) };
+        unsafe { buffered_state.rx_buf.init(rx_buffer.as_mut_ptr(), rx_len) };
 
         // clear errors
         let errors = r.errorsrc().read();
@@ -683,7 +718,9 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
         let mut ppi_ch1 = Ppi::new_one_to_one(ppi_ch1, Event::from_reg(r.events_rxdrdy()), timer.task_count());
         ppi_ch1.enable();
 
-        s.rx_ppi_ch.store(ppi_ch2.number() as u8, Ordering::Relaxed);
+        buffered_state
+            .rx_ppi_ch
+            .store(ppi_ch2.number() as u8, Ordering::Relaxed);
         let mut ppi_group = PpiGroup::new(ppi_group);
         let mut ppi_ch2 = Ppi::new_one_to_two(
             ppi_ch2,
@@ -695,11 +732,14 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
         ppi_group.add_channel(&ppi_ch2);
 
         Self {
-            _peri: peri,
+            r,
+            state,
+            buffered_state,
             timer,
             _ppi_ch1: ppi_ch1,
             _ppi_ch2: ppi_ch2,
             _ppi_group: ppi_group,
+            _p: PhantomData,
         }
     }
 
@@ -714,17 +754,17 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
 
     /// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
     pub fn fill_buf(&mut self) -> impl Future<Output = Result<&'_ [u8], Error>> {
+        let r = self.r;
+        let s = self.buffered_state;
+        let ss = self.state;
+        let timer = &self.timer;
         poll_fn(move |cx| {
             compiler_fence(Ordering::SeqCst);
             //trace!("poll_read");
 
-            let r = U::regs();
-            let s = U::buffered_state();
-            let ss = U::state();
-
             // Read the RXDRDY counter.
-            T::regs().tasks_capture(0).write_value(1);
-            let mut end = T::regs().cc(0).read() as usize;
+            timer.cc(0).capture();
+            let mut end = timer.cc(0).read() as usize;
             //trace!("  rxdrdy count = {:?}", end);
 
             // We've set a compare channel that resets the counter to 0 when it reaches `len*2`.
@@ -771,24 +811,24 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
             return;
         }
 
-        let s = U::buffered_state();
+        let s = self.buffered_state;
         let mut rx = unsafe { s.rx_buf.reader() };
         rx.pop_done(amt);
-        U::regs().intenset().write(|w| w.set_rxstarted(true));
+        self.r.intenset().write(|w| w.set_rxstarted(true));
     }
 
     /// we are ready to read if there is data in the buffer
-    fn read_ready() -> Result<bool, Error> {
-        let state = U::buffered_state();
+    fn read_ready(&self) -> Result<bool, Error> {
+        let state = self.buffered_state;
         Ok(!state.rx_buf.is_empty())
     }
 }
 
-impl<'a, U: UarteInstance, T: TimerInstance> Drop for BufferedUarteRx<'a, U, T> {
+impl<'a> Drop for BufferedUarteRx<'a> {
     fn drop(&mut self) {
         self._ppi_group.disable_all();
 
-        let r = U::regs();
+        let r = self.r;
 
         self.timer.stop();
 
@@ -801,10 +841,10 @@ impl<'a, U: UarteInstance, T: TimerInstance> Drop for BufferedUarteRx<'a, U, T>
         r.tasks_stoprx().write_value(1);
         while r.events_rxto().read() == 0 {}
 
-        let s = U::buffered_state();
+        let s = self.buffered_state;
         unsafe { s.rx_buf.deinit() }
 
-        let s = U::state();
+        let s = self.state;
         drop_tx_rx(r, s);
     }
 }
@@ -818,43 +858,44 @@ mod _embedded_io {
         }
     }
 
-    impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarte<'d, U, T> {
+    impl<'d> embedded_io_async::ErrorType for BufferedUarte<'d> {
         type Error = Error;
     }
 
-    impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarteRx<'d, U, T> {
+    impl<'d> embedded_io_async::ErrorType for BufferedUarteRx<'d> {
         type Error = Error;
     }
 
-    impl<'d, U: UarteInstance> embedded_io_async::ErrorType for BufferedUarteTx<'d, U> {
+    impl<'d> embedded_io_async::ErrorType for BufferedUarteTx<'d> {
         type Error = Error;
     }
 
-    impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarte<'d, U, T> {
+    impl<'d> embedded_io_async::Read for BufferedUarte<'d> {
         async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
             self.read(buf).await
         }
     }
 
-    impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarteRx<'d, U, T> {
+    impl<'d> embedded_io_async::Read for BufferedUarteRx<'d> {
         async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
             self.read(buf).await
         }
     }
 
-    impl<'d, U: UarteInstance, T: TimerInstance + 'd> embedded_io_async::ReadReady for BufferedUarte<'d, U, T> {
+    impl<'d> embedded_io_async::ReadReady for BufferedUarte<'d> {
         fn read_ready(&mut self) -> Result<bool, Self::Error> {
-            BufferedUarteRx::<'d, U, T>::read_ready()
+            self.rx.read_ready()
         }
     }
 
-    impl<'d, U: UarteInstance, T: TimerInstance + 'd> embedded_io_async::ReadReady for BufferedUarteRx<'d, U, T> {
+    impl<'d> embedded_io_async::ReadReady for BufferedUarteRx<'d> {
         fn read_ready(&mut self) -> Result<bool, Self::Error> {
-            Self::read_ready()
+            let state = self.buffered_state;
+            Ok(!state.rx_buf.is_empty())
         }
     }
 
-    impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarte<'d, U, T> {
+    impl<'d> embedded_io_async::BufRead for BufferedUarte<'d> {
         async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
             self.fill_buf().await
         }
@@ -864,7 +905,7 @@ mod _embedded_io {
         }
     }
 
-    impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarteRx<'d, U, T> {
+    impl<'d> embedded_io_async::BufRead for BufferedUarteRx<'d> {
         async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
             self.fill_buf().await
         }
@@ -874,7 +915,7 @@ mod _embedded_io {
         }
     }
 
-    impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::Write for BufferedUarte<'d, U, T> {
+    impl<'d> embedded_io_async::Write for BufferedUarte<'d> {
         async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
             self.write(buf).await
         }
@@ -884,7 +925,7 @@ mod _embedded_io {
         }
     }
 
-    impl<'d: 'd, U: UarteInstance> embedded_io_async::Write for BufferedUarteTx<'d, U> {
+    impl<'d> embedded_io_async::Write for BufferedUarteTx<'d> {
         async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
             self.write(buf).await
         }
diff --git a/embassy-nrf/src/chips/nrf54l15_app.rs b/embassy-nrf/src/chips/nrf54l15_app.rs
index ff05bbec0..82d30104f 100644
--- a/embassy-nrf/src/chips/nrf54l15_app.rs
+++ b/embassy-nrf/src/chips/nrf54l15_app.rs
@@ -94,6 +94,7 @@ pub mod pac {
     #[cfg(feature = "_s")]
     #[doc(no_inline)]
     pub use nrf_pac::{
+        FICR_NS as FICR,
         SICR_S as SICR,
         ICACHEDATA_S as ICACHEDATA,
         ICACHEINFO_S as ICACHEINFO,
diff --git a/embassy-nrf/src/egu.rs b/embassy-nrf/src/egu.rs
index 028396c7c..666986115 100644
--- a/embassy-nrf/src/egu.rs
+++ b/embassy-nrf/src/egu.rs
@@ -10,24 +10,29 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 
 use crate::ppi::{Event, Task};
-use crate::{interrupt, pac, Peri};
+use crate::{Peri, interrupt, pac};
 
 /// An instance of the EGU.
-pub struct Egu<'d, T: Instance> {
-    _p: Peri<'d, T>,
+pub struct Egu<'d> {
+    r: pac::egu::Egu,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Egu<'d, T> {
+impl<'d> Egu<'d> {
     /// Create a new EGU instance.
-    pub fn new(_p: Peri<'d, T>) -> Self {
-        Self { _p }
+    pub fn new<T: Instance>(_p: Peri<'d, T>) -> Self {
+        Self {
+            r: T::regs(),
+            _phantom: PhantomData,
+        }
     }
 
     /// Get a handle to a trigger for the EGU.
-    pub fn trigger(&mut self, number: TriggerNumber) -> Trigger<'d, T> {
+    pub fn trigger(&mut self, number: TriggerNumber) -> Trigger<'d> {
         Trigger {
             number,
-            _p: PhantomData,
+            r: self.r,
+            _phantom: PhantomData,
         }
     }
 }
@@ -57,36 +62,37 @@ macro_rules! impl_egu {
 }
 
 /// Represents a trigger within the EGU.
-pub struct Trigger<'d, T: Instance> {
+pub struct Trigger<'d> {
     number: TriggerNumber,
-    _p: PhantomData<&'d T>,
+    r: pac::egu::Egu,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Trigger<'d, T> {
+impl<'d> Trigger<'d> {
     /// Get task for this trigger to use with PPI.
     pub fn task(&self) -> Task<'d> {
         let nr = self.number as usize;
-        let regs = T::regs();
-        Task::from_reg(regs.tasks_trigger(nr))
+        Task::from_reg(self.r.tasks_trigger(nr))
     }
 
     /// Get event for this trigger to use with PPI.
     pub fn event(&self) -> Event<'d> {
         let nr = self.number as usize;
-        let regs = T::regs();
-        Event::from_reg(regs.events_triggered(nr))
+        Event::from_reg(self.r.events_triggered(nr))
     }
 
     /// Enable interrupts for this trigger
     pub fn enable_interrupt(&mut self) {
-        let regs = T::regs();
-        regs.intenset().modify(|w| w.set_triggered(self.number as usize, true));
+        self.r
+            .intenset()
+            .modify(|w| w.set_triggered(self.number as usize, true));
     }
 
     /// Enable interrupts for this trigger
     pub fn disable_interrupt(&mut self) {
-        let regs = T::regs();
-        regs.intenset().modify(|w| w.set_triggered(self.number as usize, false));
+        self.r
+            .intenset()
+            .modify(|w| w.set_triggered(self.number as usize, false));
     }
 }
 
diff --git a/embassy-nrf/src/embassy_net_802154_driver.rs b/embassy-nrf/src/embassy_net_802154_driver.rs
index 8662be787..4c47b7cbd 100644
--- a/embassy-nrf/src/embassy_net_802154_driver.rs
+++ b/embassy-nrf/src/embassy_net_802154_driver.rs
@@ -1,12 +1,12 @@
 //! embassy-net IEEE 802.15.4 driver
 
-use embassy_futures::select::{select3, Either3};
+use embassy_futures::select::{Either3, select3};
 use embassy_net_driver_channel::driver::LinkState;
 use embassy_net_driver_channel::{self as ch};
 use embassy_time::{Duration, Ticker};
 
-use crate::radio::ieee802154::{Packet, Radio};
 use crate::radio::InterruptHandler;
+use crate::radio::ieee802154::{Packet, Radio};
 use crate::{self as nrf, interrupt};
 
 /// MTU for the nrf radio.
@@ -32,12 +32,12 @@ impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
 /// Background runner for the driver.
 ///
 /// You must call `.run()` in a background task for the driver to operate.
-pub struct Runner<'d, T: nrf::radio::Instance> {
-    radio: nrf::radio::ieee802154::Radio<'d, T>,
+pub struct Runner<'d> {
+    radio: nrf::radio::ieee802154::Radio<'d>,
     ch: ch::Runner<'d, MTU>,
 }
 
-impl<'d, T: nrf::radio::Instance> Runner<'d, T> {
+impl<'d> Runner<'d> {
     /// Drives the radio. Needs to run to use the driver.
     pub async fn run(mut self) -> ! {
         let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
@@ -84,7 +84,7 @@ pub async fn new<'a, const N_RX: usize, const N_TX: usize, T: nrf::radio::Instan
     radio: nrf::Peri<'a, T>,
     irq: Irq,
     state: &'a mut State<N_RX, N_TX>,
-) -> Result<(Device<'a>, Runner<'a, T>), ()>
+) -> Result<(Device<'a>, Runner<'a>), ()>
 where
     Irq: interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'a,
 {
diff --git a/embassy-nrf/src/gpio.rs b/embassy-nrf/src/gpio.rs
index ab5e7ed4b..7ed3a7927 100644
--- a/embassy-nrf/src/gpio.rs
+++ b/embassy-nrf/src/gpio.rs
@@ -5,10 +5,10 @@ use core::convert::Infallible;
 use core::hint::unreachable_unchecked;
 
 use cfg_if::cfg_if;
-use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
+use embassy_hal_internal::{Peri, PeripheralType, impl_peripheral};
 
 use crate::pac;
-use crate::pac::common::{Reg, RW};
+use crate::pac::common::{RW, Reg};
 use crate::pac::gpio;
 use crate::pac::gpio::vals;
 #[cfg(not(feature = "_nrf51"))]
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 43e43f0bf..a490d5b60 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -1,10 +1,10 @@
 //! GPIO task/event (GPIOTE) driver.
 
 use core::convert::Infallible;
-use core::future::{poll_fn, Future};
+use core::future::{Future, poll_fn};
 use core::task::{Context, Poll};
 
-use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
+use embassy_hal_internal::{Peri, PeripheralType, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::gpio::{AnyPin, Flex, Input, Output, Pin as GpioPin, SealedPin as _};
diff --git a/embassy-nrf/src/i2s.rs b/embassy-nrf/src/i2s.rs
index 53de8deee..9cce9f1e8 100644
--- a/embassy-nrf/src/i2s.rs
+++ b/embassy-nrf/src/i2s.rs
@@ -6,7 +6,7 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::mem::size_of;
 use core::ops::{Deref, DerefMut};
-use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_hal_internal::drop::OnDrop;
@@ -17,7 +17,7 @@ use crate::gpio::{AnyPin, Pin as GpioPin, PselBits};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::i2s::vals;
 use crate::util::slice_in_ram_or;
-use crate::{interrupt, pac, EASY_DMA_SIZE};
+use crate::{EASY_DMA_SIZE, interrupt, pac};
 
 /// Type alias for `MultiBuffering` with 2 buffers.
 pub type DoubleBuffering<S, const NS: usize> = MultiBuffering<S, 2, NS>;
@@ -381,7 +381,7 @@ pub struct InterruptHandler<T: Instance> {
 
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
     unsafe fn on_interrupt() {
-        let device = Device::<T>::new();
+        let device = Device::new(T::regs());
         let s = T::state();
 
         if device.is_tx_ptr_updated() {
@@ -405,8 +405,9 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 }
 
 /// I2S driver.
-pub struct I2S<'d, T: Instance> {
-    i2s: Peri<'d, T>,
+pub struct I2S<'d> {
+    r: pac::i2s::I2s,
+    state: &'static State,
     mck: Option<Peri<'d, AnyPin>>,
     sck: Peri<'d, AnyPin>,
     lrck: Peri<'d, AnyPin>,
@@ -416,10 +417,10 @@ pub struct I2S<'d, T: Instance> {
     config: Config,
 }
 
-impl<'d, T: Instance> I2S<'d, T> {
+impl<'d> I2S<'d> {
     /// Create a new I2S in master mode
-    pub fn new_master(
-        i2s: Peri<'d, T>,
+    pub fn new_master<T: Instance>(
+        _i2s: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         mck: Peri<'d, impl GpioPin>,
         sck: Peri<'d, impl GpioPin>,
@@ -427,8 +428,12 @@ impl<'d, T: Instance> I2S<'d, T> {
         master_clock: MasterClock,
         config: Config,
     ) -> Self {
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
+
         Self {
-            i2s,
+            r: T::regs(),
+            state: T::state(),
             mck: Some(mck.into()),
             sck: sck.into(),
             lrck: lrck.into(),
@@ -440,15 +445,19 @@ impl<'d, T: Instance> I2S<'d, T> {
     }
 
     /// Create a new I2S in slave mode
-    pub fn new_slave(
-        i2s: Peri<'d, T>,
+    pub fn new_slave<T: Instance>(
+        _i2s: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         sck: Peri<'d, impl GpioPin>,
         lrck: Peri<'d, impl GpioPin>,
         config: Config,
     ) -> Self {
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
+
         Self {
-            i2s,
+            r: T::regs(),
+            state: T::state(),
             mck: None,
             sck: sck.into(),
             lrck: lrck.into(),
@@ -464,10 +473,13 @@ impl<'d, T: Instance> I2S<'d, T> {
         mut self,
         sdout: Peri<'d, impl GpioPin>,
         buffers: MultiBuffering<S, NB, NS>,
-    ) -> OutputStream<'d, T, S, NB, NS> {
+    ) -> OutputStream<'d, S, NB, NS> {
         self.sdout = Some(sdout.into());
+        let p = self.build();
         OutputStream {
-            _p: self.build(),
+            r: p.0,
+            state: p.1,
+            _phantom: PhantomData,
             buffers,
         }
     }
@@ -477,11 +489,14 @@ impl<'d, T: Instance> I2S<'d, T> {
         mut self,
         sdin: Peri<'d, impl GpioPin>,
         buffers: MultiBuffering<S, NB, NS>,
-    ) -> InputStream<'d, T, S, NB, NS> {
+    ) -> InputStream<'d, S, NB, NS> {
         self.sdin = Some(sdin.into());
+        let p = self.build();
         InputStream {
-            _p: self.build(),
+            r: p.0,
+            state: p.1,
             buffers,
+            _phantom: PhantomData,
         }
     }
 
@@ -492,30 +507,33 @@ impl<'d, T: Instance> I2S<'d, T> {
         sdout: Peri<'d, impl GpioPin>,
         buffers_out: MultiBuffering<S, NB, NS>,
         buffers_in: MultiBuffering<S, NB, NS>,
-    ) -> FullDuplexStream<'d, T, S, NB, NS> {
+    ) -> FullDuplexStream<'d, S, NB, NS> {
         self.sdout = Some(sdout.into());
         self.sdin = Some(sdin.into());
+        let p = self.build();
 
         FullDuplexStream {
-            _p: self.build(),
+            r: p.0,
+            state: p.1,
+            _phantom: PhantomData,
             buffers_out,
             buffers_in,
         }
     }
 
-    fn build(self) -> Peri<'d, T> {
+    fn build(self) -> (pac::i2s::I2s, &'static State) {
         self.apply_config();
         self.select_pins();
         self.setup_interrupt();
 
-        let device = Device::<T>::new();
+        let device = Device::new(self.r);
         device.enable();
 
-        self.i2s
+        (self.r, self.state)
     }
 
     fn apply_config(&self) {
-        let c = T::regs().config();
+        let c = self.r.config();
         match &self.master_clock {
             Some(MasterClock { freq, ratio }) => {
                 c.mode().write(|w| w.set_mode(vals::Mode::MASTER));
@@ -535,7 +553,7 @@ impl<'d, T: Instance> I2S<'d, T> {
     }
 
     fn select_pins(&self) {
-        let psel = T::regs().psel();
+        let psel = self.r.psel();
         psel.mck().write_value(self.mck.psel_bits());
         psel.sck().write_value(self.sck.psel_bits());
         psel.lrck().write_value(self.lrck.psel_bits());
@@ -544,10 +562,9 @@ impl<'d, T: Instance> I2S<'d, T> {
     }
 
     fn setup_interrupt(&self) {
-        T::Interrupt::unpend();
-        unsafe { T::Interrupt::enable() };
+        // Interrupt is already set up in constructor
 
-        let device = Device::<T>::new();
+        let device = Device::new(self.r);
         device.disable_tx_ptr_interrupt();
         device.disable_rx_ptr_interrupt();
         device.disable_stopped_interrupt();
@@ -561,16 +578,16 @@ impl<'d, T: Instance> I2S<'d, T> {
         device.enable_stopped_interrupt();
     }
 
-    async fn stop() {
+    async fn stop(r: pac::i2s::I2s, state: &State) {
         compiler_fence(Ordering::SeqCst);
 
-        let device = Device::<T>::new();
+        let device = Device::new(r);
         device.stop();
 
-        T::state().started.store(false, Ordering::Relaxed);
+        state.started.store(false, Ordering::Relaxed);
 
         poll_fn(|cx| {
-            T::state().stop_waker.register(cx.waker());
+            state.stop_waker.register(cx.waker());
 
             if device.is_stopped() {
                 trace!("STOP: Ready");
@@ -586,7 +603,7 @@ impl<'d, T: Instance> I2S<'d, T> {
         device.disable();
     }
 
-    async fn send_from_ram<S>(buffer_ptr: *const [S]) -> Result<(), Error>
+    async fn send_from_ram<S>(r: pac::i2s::I2s, state: &State, buffer_ptr: *const [S]) -> Result<(), Error>
     where
         S: Sample,
     {
@@ -596,22 +613,22 @@ impl<'d, T: Instance> I2S<'d, T> {
 
         compiler_fence(Ordering::SeqCst);
 
-        let device = Device::<T>::new();
+        let device = Device::new(r);
 
         device.update_tx(buffer_ptr)?;
 
-        Self::wait_tx_ptr_update().await;
+        Self::wait_tx_ptr_update(r, state).await;
 
         compiler_fence(Ordering::SeqCst);
 
         Ok(())
     }
 
-    async fn wait_tx_ptr_update() {
+    async fn wait_tx_ptr_update(r: pac::i2s::I2s, state: &State) {
         let drop = OnDrop::new(move || {
             trace!("TX DROP: Stopping");
 
-            let device = Device::<T>::new();
+            let device = Device::new(r);
             device.disable_tx_ptr_interrupt();
             device.reset_tx_ptr_event();
             device.disable_tx();
@@ -623,9 +640,9 @@ impl<'d, T: Instance> I2S<'d, T> {
         });
 
         poll_fn(|cx| {
-            T::state().tx_waker.register(cx.waker());
+            state.tx_waker.register(cx.waker());
 
-            let device = Device::<T>::new();
+            let device = Device::new(r);
             if device.is_tx_ptr_updated() {
                 trace!("TX POLL: Ready");
                 device.reset_tx_ptr_event();
@@ -641,7 +658,7 @@ impl<'d, T: Instance> I2S<'d, T> {
         drop.defuse();
     }
 
-    async fn receive_from_ram<S>(buffer_ptr: *mut [S]) -> Result<(), Error>
+    async fn receive_from_ram<S>(r: pac::i2s::I2s, state: &State, buffer_ptr: *mut [S]) -> Result<(), Error>
     where
         S: Sample,
     {
@@ -652,22 +669,22 @@ impl<'d, T: Instance> I2S<'d, T> {
 
         compiler_fence(Ordering::SeqCst);
 
-        let device = Device::<T>::new();
+        let device = Device::new(r);
 
         device.update_rx(buffer_ptr)?;
 
-        Self::wait_rx_ptr_update().await;
+        Self::wait_rx_ptr_update(r, state).await;
 
         compiler_fence(Ordering::SeqCst);
 
         Ok(())
     }
 
-    async fn wait_rx_ptr_update() {
+    async fn wait_rx_ptr_update(r: pac::i2s::I2s, state: &State) {
         let drop = OnDrop::new(move || {
             trace!("RX DROP: Stopping");
 
-            let device = Device::<T>::new();
+            let device = Device::new(r);
             device.disable_rx_ptr_interrupt();
             device.reset_rx_ptr_event();
             device.disable_rx();
@@ -679,9 +696,9 @@ impl<'d, T: Instance> I2S<'d, T> {
         });
 
         poll_fn(|cx| {
-            T::state().rx_waker.register(cx.waker());
+            state.rx_waker.register(cx.waker());
 
-            let device = Device::<T>::new();
+            let device = Device::new(r);
             if device.is_rx_ptr_updated() {
                 trace!("RX POLL: Ready");
                 device.reset_rx_ptr_event();
@@ -699,12 +716,14 @@ impl<'d, T: Instance> I2S<'d, T> {
 }
 
 /// I2S output
-pub struct OutputStream<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> {
-    _p: Peri<'d, T>,
+pub struct OutputStream<'d, S: Sample, const NB: usize, const NS: usize> {
+    r: pac::i2s::I2s,
+    state: &'static State,
     buffers: MultiBuffering<S, NB, NS>,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> OutputStream<'d, T, S, NB, NS> {
+impl<'d, S: Sample, const NB: usize, const NS: usize> OutputStream<'d, S, NB, NS> {
     /// Get a mutable reference to the current buffer.
     pub fn buffer(&mut self) -> &mut [S] {
         self.buffers.get_mut()
@@ -715,10 +734,9 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> OutputStream<
     where
         S: Sample,
     {
-        let device = Device::<T>::new();
+        let device = Device::new(self.r);
 
-        let s = T::state();
-        if s.started.load(Ordering::Relaxed) {
+        if self.state.started.load(Ordering::Relaxed) {
             self.stop().await;
         }
 
@@ -727,11 +745,11 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> OutputStream<
 
         device.update_tx(self.buffers.switch())?;
 
-        s.started.store(true, Ordering::Relaxed);
+        self.state.started.store(true, Ordering::Relaxed);
 
         device.start();
 
-        I2S::<T>::wait_tx_ptr_update().await;
+        I2S::wait_tx_ptr_update(self.r, self.state).await;
 
         Ok(())
     }
@@ -739,7 +757,7 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> OutputStream<
     /// Stops the I2S transfer and waits until it has stopped.
     #[inline(always)]
     pub async fn stop(&self) {
-        I2S::<T>::stop().await
+        I2S::stop(self.r, self.state).await
     }
 
     /// Sends the current buffer for transmission in the DMA.
@@ -748,17 +766,19 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> OutputStream<
     where
         S: Sample,
     {
-        I2S::<T>::send_from_ram(self.buffers.switch()).await
+        I2S::send_from_ram(self.r, self.state, self.buffers.switch()).await
     }
 }
 
 /// I2S input
-pub struct InputStream<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> {
-    _p: Peri<'d, T>,
+pub struct InputStream<'d, S: Sample, const NB: usize, const NS: usize> {
+    r: pac::i2s::I2s,
+    state: &'static State,
     buffers: MultiBuffering<S, NB, NS>,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> InputStream<'d, T, S, NB, NS> {
+impl<'d, S: Sample, const NB: usize, const NS: usize> InputStream<'d, S, NB, NS> {
     /// Get a mutable reference to the current buffer.
     pub fn buffer(&mut self) -> &mut [S] {
         self.buffers.get_mut()
@@ -769,10 +789,9 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> InputStream<'
     where
         S: Sample,
     {
-        let device = Device::<T>::new();
+        let device = Device::new(self.r);
 
-        let s = T::state();
-        if s.started.load(Ordering::Relaxed) {
+        if self.state.started.load(Ordering::Relaxed) {
             self.stop().await;
         }
 
@@ -781,11 +800,11 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> InputStream<'
 
         device.update_rx(self.buffers.switch())?;
 
-        s.started.store(true, Ordering::Relaxed);
+        self.state.started.store(true, Ordering::Relaxed);
 
         device.start();
 
-        I2S::<T>::wait_rx_ptr_update().await;
+        I2S::wait_rx_ptr_update(self.r, self.state).await;
 
         Ok(())
     }
@@ -793,7 +812,7 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> InputStream<'
     /// Stops the I2S transfer and waits until it has stopped.
     #[inline(always)]
     pub async fn stop(&self) {
-        I2S::<T>::stop().await
+        I2S::stop(self.r, self.state).await
     }
 
     /// Sets the current buffer for reception from the DMA.
@@ -803,18 +822,20 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> InputStream<'
     where
         S: Sample,
     {
-        I2S::<T>::receive_from_ram(self.buffers.switch_mut()).await
+        I2S::receive_from_ram(self.r, self.state, self.buffers.switch_mut()).await
     }
 }
 
 /// I2S full duplex stream (input & output)
-pub struct FullDuplexStream<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> {
-    _p: Peri<'d, T>,
+pub struct FullDuplexStream<'d, S: Sample, const NB: usize, const NS: usize> {
+    r: pac::i2s::I2s,
+    state: &'static State,
     buffers_out: MultiBuffering<S, NB, NS>,
     buffers_in: MultiBuffering<S, NB, NS>,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> FullDuplexStream<'d, T, S, NB, NS> {
+impl<'d, S: Sample, const NB: usize, const NS: usize> FullDuplexStream<'d, S, NB, NS> {
     /// Get the current output and input buffers.
     pub fn buffers(&mut self) -> (&mut [S], &[S]) {
         (self.buffers_out.get_mut(), self.buffers_in.get())
@@ -825,10 +846,9 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> FullDuplexStr
     where
         S: Sample,
     {
-        let device = Device::<T>::new();
+        let device = Device::new(self.r);
 
-        let s = T::state();
-        if s.started.load(Ordering::Relaxed) {
+        if self.state.started.load(Ordering::Relaxed) {
             self.stop().await;
         }
 
@@ -839,12 +859,12 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> FullDuplexStr
         device.update_tx(self.buffers_out.switch())?;
         device.update_rx(self.buffers_in.switch_mut())?;
 
-        s.started.store(true, Ordering::Relaxed);
+        self.state.started.store(true, Ordering::Relaxed);
 
         device.start();
 
-        I2S::<T>::wait_tx_ptr_update().await;
-        I2S::<T>::wait_rx_ptr_update().await;
+        I2S::wait_tx_ptr_update(self.r, self.state).await;
+        I2S::wait_rx_ptr_update(self.r, self.state).await;
 
         Ok(())
     }
@@ -852,7 +872,7 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> FullDuplexStr
     /// Stops the I2S transfer and waits until it has stopped.
     #[inline(always)]
     pub async fn stop(&self) {
-        I2S::<T>::stop().await
+        I2S::stop(self.r, self.state).await
     }
 
     /// Sets the current buffers for output and input for transmission/reception from the DMA.
@@ -861,18 +881,18 @@ impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> FullDuplexStr
     where
         S: Sample,
     {
-        I2S::<T>::send_from_ram(self.buffers_out.switch()).await?;
-        I2S::<T>::receive_from_ram(self.buffers_in.switch_mut()).await?;
+        I2S::send_from_ram(self.r, self.state, self.buffers_out.switch()).await?;
+        I2S::receive_from_ram(self.r, self.state, self.buffers_in.switch_mut()).await?;
         Ok(())
     }
 }
 
 /// Helper encapsulating common I2S device operations.
-struct Device<T>(pac::i2s::I2s, PhantomData<T>);
+struct Device(pac::i2s::I2s);
 
-impl<T: Instance> Device<T> {
-    fn new() -> Self {
-        Self(T::regs(), PhantomData)
+impl Device {
+    fn new(r: pac::i2s::I2s) -> Self {
+        Self(r)
     }
 
     #[inline(always)]
diff --git a/embassy-nrf/src/ipc.rs b/embassy-nrf/src/ipc.rs
index a8a08c911..a40c36c99 100644
--- a/embassy-nrf/src/ipc.rs
+++ b/embassy-nrf/src/ipc.rs
@@ -134,97 +134,99 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 
 /// IPC driver
 #[non_exhaustive]
-pub struct Ipc<'d, T: Instance> {
+pub struct Ipc<'d> {
     /// Event 0
-    pub event0: Event<'d, T>,
+    pub event0: Event<'d>,
     /// Event 1
-    pub event1: Event<'d, T>,
+    pub event1: Event<'d>,
     /// Event 2
-    pub event2: Event<'d, T>,
+    pub event2: Event<'d>,
     /// Event 3
-    pub event3: Event<'d, T>,
+    pub event3: Event<'d>,
     /// Event 4
-    pub event4: Event<'d, T>,
+    pub event4: Event<'d>,
     /// Event 5
-    pub event5: Event<'d, T>,
+    pub event5: Event<'d>,
     /// Event 6
-    pub event6: Event<'d, T>,
+    pub event6: Event<'d>,
     /// Event 7
-    pub event7: Event<'d, T>,
+    pub event7: Event<'d>,
     /// Event 8
-    pub event8: Event<'d, T>,
+    pub event8: Event<'d>,
     /// Event 9
-    pub event9: Event<'d, T>,
+    pub event9: Event<'d>,
     /// Event 10
-    pub event10: Event<'d, T>,
+    pub event10: Event<'d>,
     /// Event 11
-    pub event11: Event<'d, T>,
+    pub event11: Event<'d>,
     /// Event 12
-    pub event12: Event<'d, T>,
+    pub event12: Event<'d>,
     /// Event 13
-    pub event13: Event<'d, T>,
+    pub event13: Event<'d>,
     /// Event 14
-    pub event14: Event<'d, T>,
+    pub event14: Event<'d>,
     /// Event 15
-    pub event15: Event<'d, T>,
+    pub event15: Event<'d>,
 }
 
-impl<'d, T: Instance> Ipc<'d, T> {
+impl<'d> Ipc<'d> {
     /// Create a new IPC driver.
-    pub fn new(
+    pub fn new<T: Instance>(
         _p: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
         T::Interrupt::unpend();
         unsafe { T::Interrupt::enable() };
 
-        let _phantom = PhantomData;
+        let r = T::regs();
+        let state = T::state();
         #[rustfmt::skip]
-        let r = Self { // attributes on expressions are experimental
-            event0: Event { number: EventNumber::Event0, _phantom },
-            event1: Event { number: EventNumber::Event1, _phantom },
-            event2: Event { number: EventNumber::Event2, _phantom },
-            event3: Event { number: EventNumber::Event3, _phantom },
-            event4: Event { number: EventNumber::Event4, _phantom },
-            event5: Event { number: EventNumber::Event5, _phantom },
-            event6: Event { number: EventNumber::Event6, _phantom },
-            event7: Event { number: EventNumber::Event7, _phantom },
-            event8: Event { number: EventNumber::Event8, _phantom },
-            event9: Event { number: EventNumber::Event9, _phantom },
-            event10: Event { number: EventNumber::Event10, _phantom },
-            event11: Event { number: EventNumber::Event11, _phantom },
-            event12: Event { number: EventNumber::Event12, _phantom },
-            event13: Event { number: EventNumber::Event13, _phantom },
-            event14: Event { number: EventNumber::Event14, _phantom },
-            event15: Event { number: EventNumber::Event15, _phantom },
+        let result = Self { // attributes on expressions are experimental
+            event0: Event { number: EventNumber::Event0, r, state, _phantom: PhantomData },
+            event1: Event { number: EventNumber::Event1, r, state, _phantom: PhantomData },
+            event2: Event { number: EventNumber::Event2, r, state, _phantom: PhantomData },
+            event3: Event { number: EventNumber::Event3, r, state, _phantom: PhantomData },
+            event4: Event { number: EventNumber::Event4, r, state, _phantom: PhantomData },
+            event5: Event { number: EventNumber::Event5, r, state, _phantom: PhantomData },
+            event6: Event { number: EventNumber::Event6, r, state, _phantom: PhantomData },
+            event7: Event { number: EventNumber::Event7, r, state, _phantom: PhantomData },
+            event8: Event { number: EventNumber::Event8, r, state, _phantom: PhantomData },
+            event9: Event { number: EventNumber::Event9, r, state, _phantom: PhantomData },
+            event10: Event { number: EventNumber::Event10, r, state, _phantom: PhantomData },
+            event11: Event { number: EventNumber::Event11, r, state, _phantom: PhantomData },
+            event12: Event { number: EventNumber::Event12, r, state, _phantom: PhantomData },
+            event13: Event { number: EventNumber::Event13, r, state, _phantom: PhantomData },
+            event14: Event { number: EventNumber::Event14, r, state, _phantom: PhantomData },
+            event15: Event { number: EventNumber::Event15, r, state, _phantom: PhantomData },
         };
-        r
+        result
     }
 }
 
 /// IPC event
-pub struct Event<'d, T: Instance> {
+pub struct Event<'d> {
     number: EventNumber,
-    _phantom: PhantomData<&'d T>,
+    r: pac::ipc::Ipc,
+    state: &'static State,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Event<'d, T> {
+impl<'d> Event<'d> {
     /// Trigger the event.
     pub fn trigger(&self) {
         let nr = self.number;
-        T::regs().tasks_send(nr as usize).write_value(1);
+        self.r.tasks_send(nr as usize).write_value(1);
     }
 
     /// Wait for the event to be triggered.
     pub async fn wait(&mut self) {
-        let regs = T::regs();
         let nr = self.number as usize;
-        regs.intenset().write(|w| w.0 = 1 << nr);
+        self.r.intenset().write(|w| w.0 = 1 << nr);
         poll_fn(|cx| {
-            T::state().wakers[nr].register(cx.waker());
+            self.state.wakers[nr].register(cx.waker());
 
-            if regs.events_receive(nr).read() == 1 {
-                regs.events_receive(nr).write_value(0x00);
+            if self.r.events_receive(nr).read() == 1 {
+                self.r.events_receive(nr).write_value(0x00);
                 Poll::Ready(())
             } else {
                 Poll::Pending
@@ -239,16 +241,17 @@ impl<'d, T: Instance> Event<'d, T> {
     }
 
     /// Create a handle that can trigger the event.
-    pub fn trigger_handle(&self) -> EventTrigger<'d, T> {
+    pub fn trigger_handle(&self) -> EventTrigger<'d> {
         EventTrigger {
             number: self.number,
+            r: self.r,
             _phantom: PhantomData,
         }
     }
 
     /// Configure the channels the event will broadcast to
     pub fn configure_trigger<I: IntoIterator<Item = IpcChannel>>(&mut self, channels: I) {
-        T::regs().send_cnf(self.number as usize).write(|w| {
+        self.r.send_cnf(self.number as usize).write(|w| {
             for channel in channels {
                 w.0 |= channel.mask();
             }
@@ -257,7 +260,7 @@ impl<'d, T: Instance> Event<'d, T> {
 
     /// Configure the channels the event will listen on
     pub fn configure_wait<I: IntoIterator<Item = IpcChannel>>(&mut self, channels: I) {
-        T::regs().receive_cnf(self.number as usize).write(|w| {
+        self.r.receive_cnf(self.number as usize).write(|w| {
             for channel in channels {
                 w.0 |= channel.mask();
             }
@@ -267,22 +270,25 @@ impl<'d, T: Instance> Event<'d, T> {
     /// Get the task for the IPC event to use with PPI.
     pub fn task(&self) -> ppi::Task<'d> {
         let nr = self.number as usize;
-        let regs = T::regs();
-        ppi::Task::from_reg(regs.tasks_send(nr))
+        ppi::Task::from_reg(self.r.tasks_send(nr))
     }
 
     /// Get the event for the IPC event to use with PPI.
     pub fn event(&self) -> ppi::Event<'d> {
         let nr = self.number as usize;
-        let regs = T::regs();
-        ppi::Event::from_reg(regs.events_receive(nr))
+        ppi::Event::from_reg(self.r.events_receive(nr))
     }
 
     /// Reborrow into a "child" Event.
     ///
     /// `self` will stay borrowed until the child Event is dropped.
-    pub fn reborrow(&mut self) -> Event<'_, T> {
-        Self { ..*self }
+    pub fn reborrow(&mut self) -> Event<'_> {
+        Event {
+            number: self.number,
+            r: self.r,
+            state: self.state,
+            _phantom: PhantomData,
+        }
     }
 
     /// Steal an IPC event by number.
@@ -290,9 +296,11 @@ impl<'d, T: Instance> Event<'d, T> {
     /// # Safety
     ///
     /// The event number must not be in use by another [`Event`].
-    pub unsafe fn steal(number: EventNumber) -> Self {
+    pub unsafe fn steal<T: Instance>(number: EventNumber) -> Self {
         Self {
             number,
+            r: T::regs(),
+            state: T::state(),
             _phantom: PhantomData,
         }
     }
@@ -301,17 +309,17 @@ impl<'d, T: Instance> Event<'d, T> {
 /// A handle that can trigger an IPC event.
 ///
 /// This `struct` is returned by [`Event::trigger_handle`].
-#[derive(Debug, Copy, Clone)]
-pub struct EventTrigger<'d, T: Instance> {
+pub struct EventTrigger<'d> {
     number: EventNumber,
-    _phantom: PhantomData<&'d T>,
+    r: pac::ipc::Ipc,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<T: Instance> EventTrigger<'_, T> {
+impl EventTrigger<'_> {
     /// Trigger the event.
     pub fn trigger(&self) {
         let nr = self.number;
-        T::regs().tasks_send(nr as usize).write_value(1);
+        self.r.tasks_send(nr as usize).write_value(1);
     }
 
     /// Returns the [`EventNumber`] of the event.
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 7c26a6184..1b7fb7e7f 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -1,5 +1,6 @@
 #![no_std]
 #![allow(async_fn_in_trait)]
+#![allow(unsafe_op_in_unsafe_fn)]
 #![cfg_attr(
     docsrs,
     doc = "<div style='padding:30px;background:#810;color:#fff;text-align:center;'><p>You might want to <a href='https://docs.embassy.dev/embassy-nrf'>browse the `embassy-nrf` documentation on the Embassy website</a> instead.</p><p>The documentation here on `docs.rs` is built for a single chip only (nRF52840 in particular), while on the Embassy website you can pick your exact chip from the top menu. Available peripherals and their APIs change depending on the chip.</p></div>\n\n"
@@ -252,7 +253,7 @@ macro_rules! bind_interrupts {
 
         $(
             #[allow(non_snake_case)]
-            #[no_mangle]
+            #[unsafe(no_mangle)]
             $(#[cfg($cond_irq)])?
             unsafe extern "C" fn $irq() {
                 unsafe {
@@ -284,7 +285,7 @@ macro_rules! bind_interrupts {
 pub use chip::pac;
 #[cfg(not(feature = "unstable-pac"))]
 pub(crate) use chip::pac;
-pub use chip::{peripherals, Peripherals, EASY_DMA_SIZE};
+pub use chip::{EASY_DMA_SIZE, Peripherals, peripherals};
 pub use embassy_hal_internal::{Peri, PeripheralType};
 
 pub use crate::chip::interrupt;
@@ -406,9 +407,10 @@ pub mod config {
     /// Settings for the internal capacitors.
     #[cfg(feature = "nrf5340-app-s")]
     pub struct InternalCapacitors {
-        /// Config for the internal capacitors on pins XC1 and XC2.
+        /// Config for the internal capacitors on pins XC1 and XC2. Pass `None` to not touch it.
         pub hfxo: Option<HfxoCapacitance>,
-        /// Config for the internal capacitors between pins XL1 and XL2.
+        /// Config for the internal capacitors between pins XL1 and XL2. Pass `None` to not touch
+        /// it.
         pub lfxo: Option<LfxoCapacitance>,
     }
 
@@ -416,6 +418,8 @@ pub mod config {
     #[cfg(feature = "nrf5340-app-s")]
     #[derive(Copy, Clone)]
     pub enum HfxoCapacitance {
+        /// Use external capacitors
+        External,
         /// 7.0 pF
         _7_0pF,
         /// 7.5 pF
@@ -475,8 +479,9 @@ pub mod config {
     #[cfg(feature = "nrf5340-app-s")]
     impl HfxoCapacitance {
         /// The capacitance value times two.
-        pub(crate) const fn value2(self) -> i32 {
+        pub(crate) fn value2(self) -> i32 {
             match self {
+                HfxoCapacitance::External => unreachable!(),
                 HfxoCapacitance::_7_0pF => 14,
                 HfxoCapacitance::_7_5pF => 15,
                 HfxoCapacitance::_8_0pF => 16,
@@ -506,11 +511,17 @@ pub mod config {
                 HfxoCapacitance::_20_0pF => 40,
             }
         }
+
+        pub(crate) fn external(self) -> bool {
+            matches!(self, Self::External)
+        }
     }
 
     /// Internal capacitance value for the LFXO.
     #[cfg(feature = "nrf5340-app-s")]
     pub enum LfxoCapacitance {
+        /// Use external capacitors
+        External = 0,
         /// 6 pF
         _6pF = 1,
         /// 7 pF
@@ -523,6 +534,7 @@ pub mod config {
     impl From<LfxoCapacitance> for super::pac::oscillators::vals::Intcap {
         fn from(t: LfxoCapacitance) -> Self {
             match t {
+                LfxoCapacitance::External => Self::EXTERNAL,
                 LfxoCapacitance::_6pF => Self::C6PF,
                 LfxoCapacitance::_7pF => Self::C7PF,
                 LfxoCapacitance::_9pF => Self::C9PF,
@@ -720,6 +732,29 @@ pub fn init(config: config::Config) -> Peripherals {
         }
     }
 
+    // Apply trimming values from the FICR.
+    #[cfg(any(
+        all(feature = "_nrf5340-app", feature = "_s"),
+        all(feature = "_nrf54l", feature = "_s"),
+        feature = "_nrf5340-net",
+    ))]
+    {
+        #[cfg(feature = "_nrf5340")]
+        let n = 32;
+        #[cfg(feature = "_nrf54l")]
+        let n = 64;
+        for i in 0..n {
+            let info = pac::FICR.trimcnf(i);
+            let addr = info.addr().read();
+            if addr == 0 || addr == 0xFFFF_FFFF {
+                break;
+            }
+            unsafe {
+                (addr as *mut u32).write_volatile(info.data().read());
+            }
+        }
+    }
+
     // GLITCHDET is only accessible for secure code
     #[cfg(all(feature = "_nrf54l", feature = "_s"))]
     {
@@ -953,17 +988,21 @@ pub fn init(config: config::Config) -> Peripherals {
     #[cfg(feature = "nrf5340-app-s")]
     {
         if let Some(cap) = config.internal_capacitors.hfxo {
-            let mut slope = pac::FICR.xosc32mtrim().read().slope() as i32;
-            let offset = pac::FICR.xosc32mtrim().read().offset() as i32;
-            // slope is a signed 5-bit integer
-            if slope >= 16 {
-                slope -= 32;
+            if cap.external() {
+                pac::OSCILLATORS.xosc32mcaps().write(|w| w.set_enable(false));
+            } else {
+                let mut slope = pac::FICR.xosc32mtrim().read().slope() as i32;
+                let offset = pac::FICR.xosc32mtrim().read().offset() as i32;
+                // slope is a signed 5-bit integer
+                if slope >= 16 {
+                    slope -= 32;
+                }
+                let capvalue = (((slope + 56) * (cap.value2() - 14)) + ((offset - 8) << 4) + 32) >> 6;
+                pac::OSCILLATORS.xosc32mcaps().write(|w| {
+                    w.set_capvalue(capvalue as u8);
+                    w.set_enable(true);
+                });
             }
-            let capvalue = (((slope + 56) * (cap.value2() - 14)) + ((offset - 8) << 4) + 32) >> 6;
-            pac::OSCILLATORS.xosc32mcaps().write(|w| {
-                w.set_capvalue(capvalue as u8);
-                w.set_enable(true);
-            });
         }
         if let Some(cap) = config.internal_capacitors.lfxo {
             pac::OSCILLATORS.xosc32ki().intcap().write(|w| w.set_intcap(cap.into()));
diff --git a/embassy-nrf/src/nfct.rs b/embassy-nrf/src/nfct.rs
index 8d70ec954..bfbdc2906 100644
--- a/embassy-nrf/src/nfct.rs
+++ b/embassy-nrf/src/nfct.rs
@@ -10,18 +10,18 @@
 #![macro_use]
 
 use core::future::poll_fn;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_sync::waitqueue::AtomicWaker;
 pub use vals::{Bitframesdd as SddPat, Discardmode as DiscardMode};
 
 use crate::interrupt::InterruptExt;
-use crate::pac::nfct::vals;
 use crate::pac::NFCT;
+use crate::pac::nfct::vals;
 use crate::peripherals::NFCT;
 use crate::util::slice_in_ram;
-use crate::{interrupt, pac, Peri};
+use crate::{Peri, interrupt, pac};
 
 /// NFCID1 (aka UID) of different sizes.
 #[derive(Clone, Eq, PartialEq, Ord, PartialOrd, Hash, Debug)]
diff --git a/embassy-nrf/src/nvmc.rs b/embassy-nrf/src/nvmc.rs
index c46af0b34..3f38cd0f5 100644
--- a/embassy-nrf/src/nvmc.rs
+++ b/embassy-nrf/src/nvmc.rs
@@ -8,7 +8,7 @@ use embedded_storage::nor_flash::{
 
 use crate::pac::nvmc::vals;
 use crate::peripherals::NVMC;
-use crate::{pac, Peri};
+use crate::{Peri, pac};
 
 #[cfg(not(feature = "_nrf5340-net"))]
 /// Erase size of NVMC flash in bytes.
diff --git a/embassy-nrf/src/pdm.rs b/embassy-nrf/src/pdm.rs
index c2a4ba65f..bc28f5c8a 100644
--- a/embassy-nrf/src/pdm.rs
+++ b/embassy-nrf/src/pdm.rs
@@ -4,7 +4,7 @@
 
 use core::future::poll_fn;
 use core::marker::PhantomData;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_hal_internal::drop::OnDrop;
@@ -13,7 +13,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 use fixed::types::I7F1;
 
 use crate::chip::EASY_DMA_SIZE;
-use crate::gpio::{AnyPin, Pin as GpioPin, SealedPin, DISCONNECTED};
+use crate::gpio::{AnyPin, DISCONNECTED, Pin as GpioPin, SealedPin};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::gpio::vals as gpiovals;
 use crate::pac::pdm::vals;
@@ -53,8 +53,10 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 }
 
 /// PDM microphone interface
-pub struct Pdm<'d, T: Instance> {
-    _peri: Peri<'d, T>,
+pub struct Pdm<'d> {
+    r: pac::pdm::Pdm,
+    state: &'static State,
+    _phantom: PhantomData<&'d ()>,
 }
 
 /// PDM error
@@ -86,9 +88,9 @@ pub enum SamplerState {
     Stopped,
 }
 
-impl<'d, T: Instance> Pdm<'d, T> {
+impl<'d> Pdm<'d> {
     /// Create PDM driver
-    pub fn new(
+    pub fn new<T: Instance>(
         pdm: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         clk: Peri<'d, impl GpioPin>,
@@ -98,7 +100,7 @@ impl<'d, T: Instance> Pdm<'d, T> {
         Self::new_inner(pdm, clk.into(), din.into(), config)
     }
 
-    fn new_inner(pdm: Peri<'d, T>, clk: Peri<'d, AnyPin>, din: Peri<'d, AnyPin>, config: Config) -> Self {
+    fn new_inner<T: Instance>(_pdm: Peri<'d, T>, clk: Peri<'d, AnyPin>, din: Peri<'d, AnyPin>, config: Config) -> Self {
         let r = T::regs();
 
         // setup gpio pins
@@ -133,7 +135,11 @@ impl<'d, T: Instance> Pdm<'d, T> {
 
         r.enable().write(|w| w.set_enable(true));
 
-        Self { _peri: pdm }
+        Self {
+            r: T::regs(),
+            state: T::state(),
+            _phantom: PhantomData,
+        }
     }
 
     fn _set_gain(r: pac::pdm::Pdm, gain_left: I7F1, gain_right: I7F1) {
@@ -147,26 +153,26 @@ impl<'d, T: Instance> Pdm<'d, T> {
 
     /// Adjust the gain of the PDM microphone on the fly
     pub fn set_gain(&mut self, gain_left: I7F1, gain_right: I7F1) {
-        Self::_set_gain(T::regs(), gain_left, gain_right)
+        Self::_set_gain(self.r, gain_left, gain_right)
     }
 
     /// Start sampling microphone data into a dummy buffer.
     /// Useful to start the microphone and keep it active between recording samples.
     pub async fn start(&mut self) {
-        let r = T::regs();
-
         // start dummy sampling because microphone needs some setup time
-        r.sample().ptr().write_value(DUMMY_BUFFER.as_ptr() as u32);
-        r.sample().maxcnt().write(|w| w.set_buffsize(DUMMY_BUFFER.len() as _));
+        self.r.sample().ptr().write_value(DUMMY_BUFFER.as_ptr() as u32);
+        self.r
+            .sample()
+            .maxcnt()
+            .write(|w| w.set_buffsize(DUMMY_BUFFER.len() as _));
 
-        r.tasks_start().write_value(1);
+        self.r.tasks_start().write_value(1);
     }
 
     /// Stop sampling microphone data inta a dummy buffer
     pub async fn stop(&mut self) {
-        let r = T::regs();
-        r.tasks_stop().write_value(1);
-        r.events_started().write_value(0);
+        self.r.tasks_stop().write_value(1);
+        self.r.events_started().write_value(0);
     }
 
     /// Sample data into the given buffer
@@ -178,12 +184,11 @@ impl<'d, T: Instance> Pdm<'d, T> {
             return Err(Error::BufferTooLong);
         }
 
-        let r = T::regs();
-
-        if r.events_started().read() == 0 {
+        if self.r.events_started().read() == 0 {
             return Err(Error::NotRunning);
         }
 
+        let r = self.r;
         let drop = OnDrop::new(move || {
             r.intenclr().write(|w| w.set_end(true));
             r.events_stopped().write_value(0);
@@ -198,34 +203,37 @@ impl<'d, T: Instance> Pdm<'d, T> {
         // setup user buffer
         let ptr = buffer.as_ptr();
         let len = buffer.len();
-        r.sample().ptr().write_value(ptr as u32);
-        r.sample().maxcnt().write(|w| w.set_buffsize(len as _));
+        self.r.sample().ptr().write_value(ptr as u32);
+        self.r.sample().maxcnt().write(|w| w.set_buffsize(len as _));
 
         // wait till the current sample is finished and the user buffer sample is started
-        Self::wait_for_sample().await;
+        self.wait_for_sample().await;
 
         // reset the buffer back to the dummy buffer
-        r.sample().ptr().write_value(DUMMY_BUFFER.as_ptr() as u32);
-        r.sample().maxcnt().write(|w| w.set_buffsize(DUMMY_BUFFER.len() as _));
+        self.r.sample().ptr().write_value(DUMMY_BUFFER.as_ptr() as u32);
+        self.r
+            .sample()
+            .maxcnt()
+            .write(|w| w.set_buffsize(DUMMY_BUFFER.len() as _));
 
         // wait till the user buffer is sampled
-        Self::wait_for_sample().await;
+        self.wait_for_sample().await;
 
         drop.defuse();
 
         Ok(())
     }
 
-    async fn wait_for_sample() {
-        let r = T::regs();
-
-        r.events_end().write_value(0);
-        r.intenset().write(|w| w.set_end(true));
+    async fn wait_for_sample(&mut self) {
+        self.r.events_end().write_value(0);
+        self.r.intenset().write(|w| w.set_end(true));
 
         compiler_fence(Ordering::SeqCst);
 
+        let state = self.state;
+        let r = self.r;
         poll_fn(|cx| {
-            T::state().waker.register(cx.waker());
+            state.waker.register(cx.waker());
             if r.events_end().read() != 0 {
                 return Poll::Ready(());
             }
@@ -255,20 +263,18 @@ impl<'d, T: Instance> Pdm<'d, T> {
     where
         S: FnMut(&[i16; N]) -> SamplerState,
     {
-        let r = T::regs();
-
-        if r.events_started().read() != 0 {
+        if self.r.events_started().read() != 0 {
             return Err(Error::AlreadyRunning);
         }
 
-        r.sample().ptr().write_value(bufs[0].as_mut_ptr() as u32);
-        r.sample().maxcnt().write(|w| w.set_buffsize(N as _));
+        self.r.sample().ptr().write_value(bufs[0].as_mut_ptr() as u32);
+        self.r.sample().maxcnt().write(|w| w.set_buffsize(N as _));
 
         // Reset and enable the events
-        r.events_end().write_value(0);
-        r.events_started().write_value(0);
-        r.events_stopped().write_value(0);
-        r.intenset().write(|w| {
+        self.r.events_end().write_value(0);
+        self.r.events_started().write_value(0);
+        self.r.events_stopped().write_value(0);
+        self.r.intenset().write(|w| {
             w.set_end(true);
             w.set_started(true);
             w.set_stopped(true);
@@ -278,23 +284,24 @@ impl<'d, T: Instance> Pdm<'d, T> {
         // wouldn't happen anyway
         compiler_fence(Ordering::SeqCst);
 
-        r.tasks_start().write_value(1);
+        self.r.tasks_start().write_value(1);
 
         let mut current_buffer = 0;
 
         let mut done = false;
 
-        let drop = OnDrop::new(|| {
+        let r = self.r;
+        let drop = OnDrop::new(move || {
             r.tasks_stop().write_value(1);
             // N.B. It would be better if this were async, but Drop only support sync code
             while r.events_stopped().read() != 0 {}
         });
 
+        let state = self.state;
+        let r = self.r;
         // Wait for events and complete when the sampler indicates it has had enough
         poll_fn(|cx| {
-            let r = T::regs();
-
-            T::state().waker.register(cx.waker());
+            state.waker.register(cx.waker());
 
             if r.events_end().read() != 0 {
                 compiler_fence(Ordering::SeqCst);
@@ -411,16 +418,14 @@ impl From<Edge> for vals::Edge {
     }
 }
 
-impl<'d, T: Instance> Drop for Pdm<'d, T> {
+impl<'d> Drop for Pdm<'d> {
     fn drop(&mut self) {
-        let r = T::regs();
-
-        r.tasks_stop().write_value(1);
+        self.r.tasks_stop().write_value(1);
 
-        r.enable().write(|w| w.set_enable(false));
+        self.r.enable().write(|w| w.set_enable(false));
 
-        r.psel().din().write_value(DISCONNECTED);
-        r.psel().clk().write_value(DISCONNECTED);
+        self.r.psel().din().write_value(DISCONNECTED);
+        self.r.psel().clk().write_value(DISCONNECTED);
     }
 }
 
diff --git a/embassy-nrf/src/ppi/dppi.rs b/embassy-nrf/src/ppi/dppi.rs
index 078d2fd1c..168647be3 100644
--- a/embassy-nrf/src/ppi/dppi.rs
+++ b/embassy-nrf/src/ppi/dppi.rs
@@ -1,5 +1,5 @@
 use super::{Channel, ConfigurableChannel, Event, Ppi, Task};
-use crate::{pac, Peri};
+use crate::{Peri, pac};
 
 const DPPI_ENABLE_BIT: u32 = 0x8000_0000;
 const DPPI_CHANNEL_MASK: u32 = 0x0000_00FF;
diff --git a/embassy-nrf/src/ppi/mod.rs b/embassy-nrf/src/ppi/mod.rs
index 2bcf72e9c..f30c2218d 100644
--- a/embassy-nrf/src/ppi/mod.rs
+++ b/embassy-nrf/src/ppi/mod.rs
@@ -18,9 +18,9 @@
 use core::marker::PhantomData;
 use core::ptr::NonNull;
 
-use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
+use embassy_hal_internal::{Peri, PeripheralType, impl_peripheral};
 
-use crate::pac::common::{Reg, RW, W};
+use crate::pac::common::{RW, Reg, W};
 use crate::peripherals;
 
 #[cfg_attr(feature = "_dppi", path = "dppi.rs")]
diff --git a/embassy-nrf/src/ppi/ppi.rs b/embassy-nrf/src/ppi/ppi.rs
index 531c25444..18bc8b8db 100644
--- a/embassy-nrf/src/ppi/ppi.rs
+++ b/embassy-nrf/src/ppi/ppi.rs
@@ -1,5 +1,5 @@
 use super::{Channel, ConfigurableChannel, Event, Ppi, Task};
-use crate::{pac, Peri};
+use crate::{Peri, pac};
 
 impl<'d> Task<'d> {
     fn reg_val(&self) -> u32 {
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index d6b40b5c0..e038f44b8 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -2,11 +2,11 @@
 
 #![macro_use]
 
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 
 use embassy_hal_internal::{Peri, PeripheralType};
 
-use crate::gpio::{convert_drive, AnyPin, OutputDrive, Pin as GpioPin, PselBits, SealedPin as _, DISCONNECTED};
+use crate::gpio::{AnyPin, DISCONNECTED, OutputDrive, Pin as GpioPin, PselBits, SealedPin as _, convert_drive};
 use crate::pac::gpio::vals as gpiovals;
 use crate::pac::pwm::vals;
 use crate::ppi::{Event, Task};
@@ -15,8 +15,8 @@ use crate::{interrupt, pac};
 
 /// SimplePwm is the traditional pwm interface you're probably used to, allowing
 /// to simply set a duty cycle across up to four channels.
-pub struct SimplePwm<'d, T: Instance> {
-    _peri: Peri<'d, T>,
+pub struct SimplePwm<'d> {
+    r: pac::pwm::Pwm,
     duty: [u16; 4],
     ch0: Option<Peri<'d, AnyPin>>,
     ch1: Option<Peri<'d, AnyPin>>,
@@ -26,8 +26,8 @@ pub struct SimplePwm<'d, T: Instance> {
 
 /// SequencePwm allows you to offload the updating of a sequence of duty cycles
 /// to up to four channels, as well as repeat that sequence n times.
-pub struct SequencePwm<'d, T: Instance> {
-    _peri: Peri<'d, T>,
+pub struct SequencePwm<'d> {
+    r: pac::pwm::Pwm,
     ch0: Option<Peri<'d, AnyPin>>,
     ch1: Option<Peri<'d, AnyPin>>,
     ch2: Option<Peri<'d, AnyPin>>,
@@ -51,16 +51,16 @@ const MAX_SEQUENCE_LEN: usize = 32767;
 /// The used pwm clock frequency
 pub const PWM_CLK_HZ: u32 = 16_000_000;
 
-impl<'d, T: Instance> SequencePwm<'d, T> {
+impl<'d> SequencePwm<'d> {
     /// Create a new 1-channel PWM
     #[allow(unused_unsafe)]
-    pub fn new_1ch(pwm: Peri<'d, T>, ch0: Peri<'d, impl GpioPin>, config: Config) -> Result<Self, Error> {
+    pub fn new_1ch<T: Instance>(pwm: Peri<'d, T>, ch0: Peri<'d, impl GpioPin>, config: Config) -> Result<Self, Error> {
         Self::new_inner(pwm, Some(ch0.into()), None, None, None, config)
     }
 
     /// Create a new 2-channel PWM
     #[allow(unused_unsafe)]
-    pub fn new_2ch(
+    pub fn new_2ch<T: Instance>(
         pwm: Peri<'d, T>,
         ch0: Peri<'d, impl GpioPin>,
         ch1: Peri<'d, impl GpioPin>,
@@ -71,7 +71,7 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
 
     /// Create a new 3-channel PWM
     #[allow(unused_unsafe)]
-    pub fn new_3ch(
+    pub fn new_3ch<T: Instance>(
         pwm: Peri<'d, T>,
         ch0: Peri<'d, impl GpioPin>,
         ch1: Peri<'d, impl GpioPin>,
@@ -83,7 +83,7 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
 
     /// Create a new 4-channel PWM
     #[allow(unused_unsafe)]
-    pub fn new_4ch(
+    pub fn new_4ch<T: Instance>(
         pwm: Peri<'d, T>,
         ch0: Peri<'d, impl GpioPin>,
         ch1: Peri<'d, impl GpioPin>,
@@ -101,7 +101,7 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
         )
     }
 
-    fn new_inner(
+    fn new_inner<T: Instance>(
         _pwm: Peri<'d, T>,
         ch0: Option<Peri<'d, AnyPin>>,
         ch1: Option<Peri<'d, AnyPin>>,
@@ -174,7 +174,7 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
         r.countertop().write(|w| w.set_countertop(config.max_duty));
 
         Ok(Self {
-            _peri: _pwm,
+            r: T::regs(),
             ch0,
             ch1,
             ch2,
@@ -185,57 +185,43 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
     /// Returns reference to `Stopped` event endpoint for PPI.
     #[inline(always)]
     pub fn event_stopped(&self) -> Event<'d> {
-        let r = T::regs();
-
-        Event::from_reg(r.events_stopped())
+        Event::from_reg(self.r.events_stopped())
     }
 
     /// Returns reference to `LoopsDone` event endpoint for PPI.
     #[inline(always)]
     pub fn event_loops_done(&self) -> Event<'d> {
-        let r = T::regs();
-
-        Event::from_reg(r.events_loopsdone())
+        Event::from_reg(self.r.events_loopsdone())
     }
 
     /// Returns reference to `PwmPeriodEnd` event endpoint for PPI.
     #[inline(always)]
     pub fn event_pwm_period_end(&self) -> Event<'d> {
-        let r = T::regs();
-
-        Event::from_reg(r.events_pwmperiodend())
+        Event::from_reg(self.r.events_pwmperiodend())
     }
 
     /// Returns reference to `Seq0 End` event endpoint for PPI.
     #[inline(always)]
     pub fn event_seq_end(&self) -> Event<'d> {
-        let r = T::regs();
-
-        Event::from_reg(r.events_seqend(0))
+        Event::from_reg(self.r.events_seqend(0))
     }
 
     /// Returns reference to `Seq1 End` event endpoint for PPI.
     #[inline(always)]
     pub fn event_seq1_end(&self) -> Event<'d> {
-        let r = T::regs();
-
-        Event::from_reg(r.events_seqend(1))
+        Event::from_reg(self.r.events_seqend(1))
     }
 
     /// Returns reference to `Seq0 Started` event endpoint for PPI.
     #[inline(always)]
     pub fn event_seq0_started(&self) -> Event<'d> {
-        let r = T::regs();
-
-        Event::from_reg(r.events_seqstarted(0))
+        Event::from_reg(self.r.events_seqstarted(0))
     }
 
     /// Returns reference to `Seq1 Started` event endpoint for PPI.
     #[inline(always)]
     pub fn event_seq1_started(&self) -> Event<'d> {
-        let r = T::regs();
-
-        Event::from_reg(r.events_seqstarted(1))
+        Event::from_reg(self.r.events_seqstarted(1))
     }
 
     /// Returns reference to `Seq0 Start` task endpoint for PPI.
@@ -244,9 +230,7 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
     /// Interacting with the sequence while it runs puts it in an unknown state
     #[inline(always)]
     pub unsafe fn task_start_seq0(&self) -> Task<'d> {
-        let r = T::regs();
-
-        Task::from_reg(r.tasks_seqstart(0))
+        Task::from_reg(self.r.tasks_seqstart(0))
     }
 
     /// Returns reference to `Seq1 Started` task endpoint for PPI.
@@ -255,9 +239,7 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
     /// Interacting with the sequence while it runs puts it in an unknown state
     #[inline(always)]
     pub unsafe fn task_start_seq1(&self) -> Task<'d> {
-        let r = T::regs();
-
-        Task::from_reg(r.tasks_seqstart(1))
+        Task::from_reg(self.r.tasks_seqstart(1))
     }
 
     /// Returns reference to `NextStep` task endpoint for PPI.
@@ -266,9 +248,7 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
     /// Interacting with the sequence while it runs puts it in an unknown state
     #[inline(always)]
     pub unsafe fn task_next_step(&self) -> Task<'d> {
-        let r = T::regs();
-
-        Task::from_reg(r.tasks_nextstep())
+        Task::from_reg(self.r.tasks_nextstep())
     }
 
     /// Returns reference to `Stop` task endpoint for PPI.
@@ -277,36 +257,34 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
     /// Interacting with the sequence while it runs puts it in an unknown state
     #[inline(always)]
     pub unsafe fn task_stop(&self) -> Task<'d> {
-        let r = T::regs();
-
-        Task::from_reg(r.tasks_stop())
+        Task::from_reg(self.r.tasks_stop())
     }
 }
 
-impl<'a, T: Instance> Drop for SequencePwm<'a, T> {
+impl<'a> Drop for SequencePwm<'a> {
     fn drop(&mut self) {
-        let r = T::regs();
-
         if let Some(pin) = &self.ch0 {
             pin.set_low();
             pin.conf().write(|_| ());
-            r.psel().out(0).write_value(DISCONNECTED);
+            self.r.psel().out(0).write_value(DISCONNECTED);
         }
         if let Some(pin) = &self.ch1 {
             pin.set_low();
             pin.conf().write(|_| ());
-            r.psel().out(1).write_value(DISCONNECTED);
+            self.r.psel().out(1).write_value(DISCONNECTED);
         }
         if let Some(pin) = &self.ch2 {
             pin.set_low();
             pin.conf().write(|_| ());
-            r.psel().out(2).write_value(DISCONNECTED);
+            self.r.psel().out(2).write_value(DISCONNECTED);
         }
         if let Some(pin) = &self.ch3 {
             pin.set_low();
             pin.conf().write(|_| ());
-            r.psel().out(3).write_value(DISCONNECTED);
+            self.r.psel().out(3).write_value(DISCONNECTED);
         }
+
+        self.r.enable().write(|w| w.set_enable(false));
     }
 }
 
@@ -384,13 +362,13 @@ impl<'s> Sequence<'s> {
 /// A single sequence that can be started and stopped.
 /// Takes one sequence along with its configuration.
 #[non_exhaustive]
-pub struct SingleSequencer<'d, 's, T: Instance> {
-    sequencer: Sequencer<'d, 's, T>,
+pub struct SingleSequencer<'d, 's> {
+    sequencer: Sequencer<'d, 's>,
 }
 
-impl<'d, 's, T: Instance> SingleSequencer<'d, 's, T> {
+impl<'d, 's> SingleSequencer<'d, 's> {
     /// Create a new sequencer
-    pub fn new(pwm: &'s mut SequencePwm<'d, T>, words: &'s [u16], config: SequenceConfig) -> Self {
+    pub fn new(pwm: &'s mut SequencePwm<'d>, words: &'s [u16], config: SequenceConfig) -> Self {
         Self {
             sequencer: Sequencer::new(pwm, Sequence::new(words, config), None),
         }
@@ -423,16 +401,16 @@ impl<'d, 's, T: Instance> SingleSequencer<'d, 's, T> {
 /// In the case where no second sequence is provided then the first sequence
 /// is used.
 #[non_exhaustive]
-pub struct Sequencer<'d, 's, T: Instance> {
-    _pwm: &'s mut SequencePwm<'d, T>,
+pub struct Sequencer<'d, 's> {
+    _pwm: &'s mut SequencePwm<'d>,
     sequence0: Sequence<'s>,
     sequence1: Option<Sequence<'s>>,
 }
 
-impl<'d, 's, T: Instance> Sequencer<'d, 's, T> {
+impl<'d, 's> Sequencer<'d, 's> {
     /// Create a new double sequence. In the absence of sequence 1, sequence 0
     /// will be used twice in the one loop.
-    pub fn new(pwm: &'s mut SequencePwm<'d, T>, sequence0: Sequence<'s>, sequence1: Option<Sequence<'s>>) -> Self {
+    pub fn new(pwm: &'s mut SequencePwm<'d>, sequence0: Sequence<'s>, sequence1: Option<Sequence<'s>>) -> Self {
         Sequencer {
             _pwm: pwm,
             sequence0,
@@ -459,7 +437,7 @@ impl<'d, 's, T: Instance> Sequencer<'d, 's, T> {
 
         self.stop();
 
-        let r = T::regs();
+        let r = self._pwm.r;
 
         r.seq(0).refresh().write(|w| w.0 = sequence0.config.refresh);
         r.seq(0).enddelay().write(|w| w.0 = sequence0.config.end_delay);
@@ -499,7 +477,7 @@ impl<'d, 's, T: Instance> Sequencer<'d, 's, T> {
     /// `start` so that they may be further mutated.
     #[inline(always)]
     pub fn stop(&self) {
-        let r = T::regs();
+        let r = self._pwm.r;
 
         r.shorts().write(|_| ());
 
@@ -510,7 +488,7 @@ impl<'d, 's, T: Instance> Sequencer<'d, 's, T> {
     }
 }
 
-impl<'d, 's, T: Instance> Drop for Sequencer<'d, 's, T> {
+impl<'d, 's> Drop for Sequencer<'d, 's> {
     fn drop(&mut self) {
         self.stop();
     }
@@ -589,22 +567,22 @@ pub enum CounterMode {
     UpAndDown,
 }
 
-impl<'d, T: Instance> SimplePwm<'d, T> {
+impl<'d> SimplePwm<'d> {
     /// Create a new 1-channel PWM
     #[allow(unused_unsafe)]
-    pub fn new_1ch(pwm: Peri<'d, T>, ch0: Peri<'d, impl GpioPin>) -> Self {
+    pub fn new_1ch<T: Instance>(pwm: Peri<'d, T>, ch0: Peri<'d, impl GpioPin>) -> Self {
         unsafe { Self::new_inner(pwm, Some(ch0.into()), None, None, None) }
     }
 
     /// Create a new 2-channel PWM
     #[allow(unused_unsafe)]
-    pub fn new_2ch(pwm: Peri<'d, T>, ch0: Peri<'d, impl GpioPin>, ch1: Peri<'d, impl GpioPin>) -> Self {
+    pub fn new_2ch<T: Instance>(pwm: Peri<'d, T>, ch0: Peri<'d, impl GpioPin>, ch1: Peri<'d, impl GpioPin>) -> Self {
         Self::new_inner(pwm, Some(ch0.into()), Some(ch1.into()), None, None)
     }
 
     /// Create a new 3-channel PWM
     #[allow(unused_unsafe)]
-    pub fn new_3ch(
+    pub fn new_3ch<T: Instance>(
         pwm: Peri<'d, T>,
         ch0: Peri<'d, impl GpioPin>,
         ch1: Peri<'d, impl GpioPin>,
@@ -615,7 +593,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
 
     /// Create a new 4-channel PWM
     #[allow(unused_unsafe)]
-    pub fn new_4ch(
+    pub fn new_4ch<T: Instance>(
         pwm: Peri<'d, T>,
         ch0: Peri<'d, impl GpioPin>,
         ch1: Peri<'d, impl GpioPin>,
@@ -633,7 +611,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
         }
     }
 
-    fn new_inner(
+    fn new_inner<T: Instance>(
         _pwm: Peri<'d, T>,
         ch0: Option<Peri<'d, AnyPin>>,
         ch1: Option<Peri<'d, AnyPin>>,
@@ -656,7 +634,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
         }
 
         let pwm = Self {
-            _peri: _pwm,
+            r: T::regs(),
             ch0,
             ch1,
             ch2,
@@ -691,22 +669,19 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
     /// Returns the enable state of the pwm counter
     #[inline(always)]
     pub fn is_enabled(&self) -> bool {
-        let r = T::regs();
-        r.enable().read().enable()
+        self.r.enable().read().enable()
     }
 
     /// Enables the PWM generator.
     #[inline(always)]
     pub fn enable(&self) {
-        let r = T::regs();
-        r.enable().write(|w| w.set_enable(true));
+        self.r.enable().write(|w| w.set_enable(true));
     }
 
     /// Disables the PWM generator. Does NOT clear the last duty cycle from the pin.
     #[inline(always)]
     pub fn disable(&self) {
-        let r = T::regs();
-        r.enable().write(|w| w.set_enable(false));
+        self.r.enable().write(|w| w.set_enable(false));
     }
 
     /// Returns the current duty of the channel
@@ -716,32 +691,30 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
 
     /// Sets duty cycle (15 bit) for a PWM channel.
     pub fn set_duty(&mut self, channel: usize, duty: u16) {
-        let r = T::regs();
-
         self.duty[channel] = duty & 0x7FFF;
 
         // reload ptr in case self was moved
-        r.seq(0).ptr().write_value((self.duty).as_ptr() as u32);
+        self.r.seq(0).ptr().write_value((self.duty).as_ptr() as u32);
 
         // defensive before seqstart
         compiler_fence(Ordering::SeqCst);
 
-        r.events_seqend(0).write_value(0);
+        self.r.events_seqend(0).write_value(0);
 
         // tasks_seqstart() doesn't exist in all svds so write its bit instead
-        r.tasks_seqstart(0).write_value(1);
+        self.r.tasks_seqstart(0).write_value(1);
 
         // defensive wait until waveform is loaded after seqstart so set_duty
         // can't be called again while dma is still reading
         if self.is_enabled() {
-            while r.events_seqend(0).read() == 0 {}
+            while self.r.events_seqend(0).read() == 0 {}
         }
     }
 
     /// Sets the PWM clock prescaler.
     #[inline(always)]
     pub fn set_prescaler(&self, div: Prescaler) {
-        T::regs()
+        self.r
             .prescaler()
             .write(|w| w.set_prescaler(vals::Prescaler::from_bits(div as u8)));
     }
@@ -749,7 +722,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
     /// Gets the PWM clock prescaler.
     #[inline(always)]
     pub fn prescaler(&self) -> Prescaler {
-        match T::regs().prescaler().read().prescaler().to_bits() {
+        match self.r.prescaler().read().prescaler().to_bits() {
             0 => Prescaler::Div1,
             1 => Prescaler::Div2,
             2 => Prescaler::Div4,
@@ -765,13 +738,13 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
     /// Sets the maximum duty cycle value.
     #[inline(always)]
     pub fn set_max_duty(&self, duty: u16) {
-        T::regs().countertop().write(|w| w.set_countertop(duty.min(32767u16)));
+        self.r.countertop().write(|w| w.set_countertop(duty.min(32767u16)));
     }
 
     /// Returns the maximum duty cycle value.
     #[inline(always)]
     pub fn max_duty(&self) -> u16 {
-        T::regs().countertop().read().countertop()
+        self.r.countertop().read().countertop()
     }
 
     /// Sets the PWM output frequency.
@@ -823,9 +796,9 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
     }
 }
 
-impl<'a, T: Instance> Drop for SimplePwm<'a, T> {
+impl<'a> Drop for SimplePwm<'a> {
     fn drop(&mut self) {
-        let r = T::regs();
+        let r = &self.r;
 
         self.disable();
 
diff --git a/embassy-nrf/src/qdec.rs b/embassy-nrf/src/qdec.rs
index 69bfab0bb..0ebd7afb8 100644
--- a/embassy-nrf/src/qdec.rs
+++ b/embassy-nrf/src/qdec.rs
@@ -16,8 +16,10 @@ use crate::pac::qdec::vals;
 use crate::{interrupt, pac};
 
 /// Quadrature decoder driver.
-pub struct Qdec<'d, T: Instance> {
-    _p: Peri<'d, T>,
+pub struct Qdec<'d> {
+    r: pac::qdec::Qdec,
+    state: &'static State,
+    _phantom: PhantomData<&'d ()>,
 }
 
 /// QDEC config
@@ -59,9 +61,9 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
     }
 }
 
-impl<'d, T: Instance> Qdec<'d, T> {
+impl<'d> Qdec<'d> {
     /// Create a new QDEC.
-    pub fn new(
+    pub fn new<T: Instance>(
         qdec: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         a: Peri<'d, impl GpioPin>,
@@ -72,7 +74,7 @@ impl<'d, T: Instance> Qdec<'d, T> {
     }
 
     /// Create a new QDEC, with a pin for LED output.
-    pub fn new_with_led(
+    pub fn new_with_led<T: Instance>(
         qdec: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         a: Peri<'d, impl GpioPin>,
@@ -83,8 +85,8 @@ impl<'d, T: Instance> Qdec<'d, T> {
         Self::new_inner(qdec, a.into(), b.into(), Some(led.into()), config)
     }
 
-    fn new_inner(
-        p: Peri<'d, T>,
+    fn new_inner<T: Instance>(
+        _p: Peri<'d, T>,
         a: Peri<'d, AnyPin>,
         b: Peri<'d, AnyPin>,
         led: Option<Peri<'d, AnyPin>>,
@@ -147,7 +149,11 @@ impl<'d, T: Instance> Qdec<'d, T> {
         // Start sampling
         r.tasks_start().write_value(1);
 
-        Self { _p: p }
+        Self {
+            r: T::regs(),
+            state: T::state(),
+            _phantom: PhantomData,
+        }
     }
 
     /// Perform an asynchronous read of the decoder.
@@ -173,17 +179,18 @@ impl<'d, T: Instance> Qdec<'d, T> {
     /// # };
     /// ```
     pub async fn read(&mut self) -> i16 {
-        let t = T::regs();
-        t.intenset().write(|w| w.set_reportrdy(true));
-        t.tasks_readclracc().write_value(1);
+        self.r.intenset().write(|w| w.set_reportrdy(true));
+        self.r.tasks_readclracc().write_value(1);
 
-        poll_fn(|cx| {
-            T::state().waker.register(cx.waker());
-            if t.events_reportrdy().read() == 0 {
+        let state = self.state;
+        let r = self.r;
+        poll_fn(move |cx| {
+            state.waker.register(cx.waker());
+            if r.events_reportrdy().read() == 0 {
                 Poll::Pending
             } else {
-                t.events_reportrdy().write_value(0);
-                let acc = t.accread().read();
+                r.events_reportrdy().write_value(0);
+                let acc = r.accread().read();
                 Poll::Ready(acc as i16)
             }
         })
diff --git a/embassy-nrf/src/qspi.rs b/embassy-nrf/src/qspi.rs
index e6e829f6e..6bb7c033e 100755
--- a/embassy-nrf/src/qspi.rs
+++ b/embassy-nrf/src/qspi.rs
@@ -2,7 +2,7 @@
 
 #![macro_use]
 
-use core::future::{poll_fn, Future};
+use core::future::{Future, poll_fn};
 use core::marker::PhantomData;
 use core::ptr;
 use core::task::Poll;
@@ -138,16 +138,18 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 }
 
 /// QSPI flash driver.
-pub struct Qspi<'d, T: Instance> {
-    _peri: Peri<'d, T>,
+pub struct Qspi<'d> {
+    r: pac::qspi::Qspi,
+    state: &'static State,
     dpm_enabled: bool,
     capacity: u32,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Qspi<'d, T> {
+impl<'d> Qspi<'d> {
     /// Create a new QSPI driver.
-    pub fn new(
-        qspi: Peri<'d, T>,
+    pub fn new<T: Instance>(
+        _qspi: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         sck: Peri<'d, impl GpioPin>,
         csn: Peri<'d, impl GpioPin>,
@@ -214,9 +216,11 @@ impl<'d, T: Instance> Qspi<'d, T> {
         r.enable().write(|w| w.set_enable(true));
 
         let res = Self {
-            _peri: qspi,
+            r: T::regs(),
+            state: T::state(),
             dpm_enabled: config.deep_power_down.is_some(),
             capacity: config.capacity,
+            _phantom: PhantomData,
         };
 
         r.events_ready().write_value(0);
@@ -274,14 +278,13 @@ impl<'d, T: Instance> Qspi<'d, T> {
             }
         }
 
-        let r = T::regs();
-        r.cinstrdat0().write(|w| w.0 = dat0);
-        r.cinstrdat1().write(|w| w.0 = dat1);
+        self.r.cinstrdat0().write(|w| w.0 = dat0);
+        self.r.cinstrdat1().write(|w| w.0 = dat1);
 
-        r.events_ready().write_value(0);
-        r.intenset().write(|w| w.set_ready(true));
+        self.r.events_ready().write_value(0);
+        self.r.intenset().write(|w| w.set_ready(true));
 
-        r.cinstrconf().write(|w| {
+        self.r.cinstrconf().write(|w| {
             w.set_opcode(opcode);
             w.set_length(vals::Length::from_bits(len + 1));
             w.set_lio2(true);
@@ -295,10 +298,8 @@ impl<'d, T: Instance> Qspi<'d, T> {
     }
 
     fn custom_instruction_finish(&mut self, resp: &mut [u8]) -> Result<(), Error> {
-        let r = T::regs();
-
-        let dat0 = r.cinstrdat0().read().0;
-        let dat1 = r.cinstrdat1().read().0;
+        let dat0 = self.r.cinstrdat0().read().0;
+        let dat1 = self.r.cinstrdat1().read().0;
         for i in 0..4 {
             if i < resp.len() {
                 resp[i] = (dat0 >> (i * 8)) as u8;
@@ -313,9 +314,9 @@ impl<'d, T: Instance> Qspi<'d, T> {
     }
 
     fn wait_ready(&mut self) -> impl Future<Output = ()> {
+        let r = self.r;
+        let s = self.state;
         poll_fn(move |cx| {
-            let r = T::regs();
-            let s = T::state();
             s.waker.register(cx.waker());
             if r.events_ready().read() != 0 {
                 return Poll::Ready(());
@@ -326,7 +327,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
 
     fn blocking_wait_ready() {
         loop {
-            let r = T::regs();
+            let r = pac::QSPI;
             if r.events_ready().read() != 0 {
                 break;
             }
@@ -339,15 +340,13 @@ impl<'d, T: Instance> Qspi<'d, T> {
         assert_eq!(data.len() as u32 % 4, 0);
         assert_eq!(address % 4, 0);
 
-        let r = T::regs();
-
-        r.read().src().write_value(address);
-        r.read().dst().write_value(data.as_ptr() as u32);
-        r.read().cnt().write(|w| w.set_cnt(data.len() as u32));
+        self.r.read().src().write_value(address);
+        self.r.read().dst().write_value(data.as_ptr() as u32);
+        self.r.read().cnt().write(|w| w.set_cnt(data.len() as u32));
 
-        r.events_ready().write_value(0);
-        r.intenset().write(|w| w.set_ready(true));
-        r.tasks_readstart().write_value(1);
+        self.r.events_ready().write_value(0);
+        self.r.intenset().write(|w| w.set_ready(true));
+        self.r.tasks_readstart().write_value(1);
 
         Ok(())
     }
@@ -358,14 +357,13 @@ impl<'d, T: Instance> Qspi<'d, T> {
         assert_eq!(data.len() as u32 % 4, 0);
         assert_eq!(address % 4, 0);
 
-        let r = T::regs();
-        r.write().src().write_value(data.as_ptr() as u32);
-        r.write().dst().write_value(address);
-        r.write().cnt().write(|w| w.set_cnt(data.len() as u32));
+        self.r.write().src().write_value(data.as_ptr() as u32);
+        self.r.write().dst().write_value(address);
+        self.r.write().cnt().write(|w| w.set_cnt(data.len() as u32));
 
-        r.events_ready().write_value(0);
-        r.intenset().write(|w| w.set_ready(true));
-        r.tasks_writestart().write_value(1);
+        self.r.events_ready().write_value(0);
+        self.r.intenset().write(|w| w.set_ready(true));
+        self.r.tasks_writestart().write_value(1);
 
         Ok(())
     }
@@ -374,13 +372,12 @@ impl<'d, T: Instance> Qspi<'d, T> {
         // TODO: Return these as errors instead.
         assert_eq!(address % 4096, 0);
 
-        let r = T::regs();
-        r.erase().ptr().write_value(address);
-        r.erase().len().write(|w| w.set_len(vals::Len::_4KB));
+        self.r.erase().ptr().write_value(address);
+        self.r.erase().len().write(|w| w.set_len(vals::Len::_4KB));
 
-        r.events_ready().write_value(0);
-        r.intenset().write(|w| w.set_ready(true));
-        r.tasks_erasestart().write_value(1);
+        self.r.events_ready().write_value(0);
+        self.r.intenset().write(|w| w.set_ready(true));
+        self.r.tasks_erasestart().write_value(1);
 
         Ok(())
     }
@@ -520,19 +517,17 @@ impl<'d, T: Instance> Qspi<'d, T> {
     }
 }
 
-impl<'d, T: Instance> Drop for Qspi<'d, T> {
+impl<'d> Drop for Qspi<'d> {
     fn drop(&mut self) {
-        let r = T::regs();
-
         if self.dpm_enabled {
             trace!("qspi: doing deep powerdown...");
 
-            r.ifconfig1().modify(|w| w.set_dpmen(true));
+            self.r.ifconfig1().modify(|w| w.set_dpmen(true));
 
             // Wait for DPM enter.
             // Unfortunately we must spin. There's no way to do this interrupt-driven.
             // The READY event does NOT fire on DPM enter (but it does fire on DPM exit :shrug:)
-            while !r.status().read().dpm() {}
+            while !self.r.status().read().dpm() {}
 
             // Wait MORE for DPM enter.
             // I have absolutely no idea why, but the wait above is not enough :'(
@@ -541,29 +536,29 @@ impl<'d, T: Instance> Drop for Qspi<'d, T> {
         }
 
         // it seems events_ready is not generated in response to deactivate. nrfx doesn't wait for it.
-        r.tasks_deactivate().write_value(1);
+        self.r.tasks_deactivate().write_value(1);
 
         // Workaround https://docs.nordicsemi.com/bundle/errata_nRF52840_Rev3/page/ERR/nRF52840/Rev3/latest/anomaly_840_122.html
         // Note that the doc has 2 register writes, but the first one is really the write to tasks_deactivate,
         // so we only do the second one here.
         unsafe { ptr::write_volatile(0x40029054 as *mut u32, 1) }
 
-        r.enable().write(|w| w.set_enable(false));
+        self.r.enable().write(|w| w.set_enable(false));
 
         // Note: we do NOT deconfigure CSN here. If DPM is in use and we disconnect CSN,
         // leaving it floating, the flash chip might read it as zero which would cause it to
         // spuriously exit DPM.
-        gpio::deconfigure_pin(r.psel().sck().read());
-        gpio::deconfigure_pin(r.psel().io0().read());
-        gpio::deconfigure_pin(r.psel().io1().read());
-        gpio::deconfigure_pin(r.psel().io2().read());
-        gpio::deconfigure_pin(r.psel().io3().read());
+        gpio::deconfigure_pin(self.r.psel().sck().read());
+        gpio::deconfigure_pin(self.r.psel().io0().read());
+        gpio::deconfigure_pin(self.r.psel().io1().read());
+        gpio::deconfigure_pin(self.r.psel().io2().read());
+        gpio::deconfigure_pin(self.r.psel().io3().read());
 
         trace!("qspi: dropped");
     }
 }
 
-impl<'d, T: Instance> ErrorType for Qspi<'d, T> {
+impl<'d> ErrorType for Qspi<'d> {
     type Error = Error;
 }
 
@@ -573,7 +568,7 @@ impl NorFlashError for Error {
     }
 }
 
-impl<'d, T: Instance> ReadNorFlash for Qspi<'d, T> {
+impl<'d> ReadNorFlash for Qspi<'d> {
     const READ_SIZE: usize = 4;
 
     fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
@@ -586,7 +581,7 @@ impl<'d, T: Instance> ReadNorFlash for Qspi<'d, T> {
     }
 }
 
-impl<'d, T: Instance> NorFlash for Qspi<'d, T> {
+impl<'d> NorFlash for Qspi<'d> {
     const WRITE_SIZE: usize = 4;
     const ERASE_SIZE: usize = 4096;
 
@@ -604,14 +599,14 @@ impl<'d, T: Instance> NorFlash for Qspi<'d, T> {
 }
 
 #[cfg(feature = "qspi-multiwrite-flash")]
-impl<'d, T: Instance> embedded_storage::nor_flash::MultiwriteNorFlash for Qspi<'d, T> {}
+impl<'d> embedded_storage::nor_flash::MultiwriteNorFlash for Qspi<'d> {}
 
 mod _eh1 {
     use embedded_storage_async::nor_flash::{NorFlash as AsyncNorFlash, ReadNorFlash as AsyncReadNorFlash};
 
     use super::*;
 
-    impl<'d, T: Instance> AsyncNorFlash for Qspi<'d, T> {
+    impl<'d> AsyncNorFlash for Qspi<'d> {
         const WRITE_SIZE: usize = <Self as NorFlash>::WRITE_SIZE;
         const ERASE_SIZE: usize = <Self as NorFlash>::ERASE_SIZE;
 
@@ -627,7 +622,7 @@ mod _eh1 {
         }
     }
 
-    impl<'d, T: Instance> AsyncReadNorFlash for Qspi<'d, T> {
+    impl<'d> AsyncReadNorFlash for Qspi<'d> {
         const READ_SIZE: usize = 4;
         async fn read(&mut self, address: u32, data: &mut [u8]) -> Result<(), Self::Error> {
             self.read(address, data).await
@@ -639,7 +634,7 @@ mod _eh1 {
     }
 
     #[cfg(feature = "qspi-multiwrite-flash")]
-    impl<'d, T: Instance> embedded_storage_async::nor_flash::MultiwriteNorFlash for Qspi<'d, T> {}
+    impl<'d> embedded_storage_async::nor_flash::MultiwriteNorFlash for Qspi<'d> {}
 }
 
 /// Peripheral static state
diff --git a/embassy-nrf/src/radio/ieee802154.rs b/embassy-nrf/src/radio/ieee802154.rs
index 7f4f8f462..54b463343 100644
--- a/embassy-nrf/src/radio/ieee802154.rs
+++ b/embassy-nrf/src/radio/ieee802154.rs
@@ -1,16 +1,18 @@
 //! IEEE 802.15.4 radio driver
 
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_hal_internal::drop::OnDrop;
 
-use super::{Error, Instance, InterruptHandler, TxPower};
+use super::{Error, InterruptHandler, TxPower};
+use crate::Peri;
 use crate::interrupt::typelevel::Interrupt;
 use crate::interrupt::{self};
 use crate::pac::radio::vals;
 pub use crate::pac::radio::vals::State as RadioState;
-use crate::Peri;
+use crate::radio::Instance;
 
 /// Default (IEEE compliant) Start of Frame Delimiter
 pub const DEFAULT_SFD: u8 = 0xA7;
@@ -32,22 +34,25 @@ pub enum Cca {
 }
 
 /// IEEE 802.15.4 radio driver.
-pub struct Radio<'d, T: Instance> {
-    _p: Peri<'d, T>,
+pub struct Radio<'d> {
+    r: crate::pac::radio::Radio,
+    state: &'static crate::radio::State,
     needs_enable: bool,
+    phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Radio<'d, T> {
+impl<'d> Radio<'d> {
     /// Create a new IEEE 802.15.4 radio driver.
-    pub fn new(
-        radio: Peri<'d, T>,
+    pub fn new<T: Instance>(
+        _radio: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
-        let r = T::regs();
+        let r = crate::pac::RADIO;
 
         // Disable and enable to reset peripheral
         r.power().write(|w| w.set_power(false));
         r.power().write(|w| w.set_power(true));
+        errata::post_power();
 
         // Enable 802.15.4 mode
         r.mode().write(|w| w.set_mode(vals::Mode::IEEE802154_250KBIT));
@@ -89,12 +94,14 @@ impl<'d, T: Instance> Radio<'d, T> {
         });
 
         // Enable NVIC interrupt
-        T::Interrupt::unpend();
-        unsafe { T::Interrupt::enable() };
+        crate::interrupt::typelevel::RADIO::unpend();
+        unsafe { crate::interrupt::typelevel::RADIO::enable() };
 
         let mut radio = Self {
-            _p: radio,
+            r: crate::pac::RADIO,
+            state: T::state(),
             needs_enable: false,
+            phantom: PhantomData,
         };
 
         radio.set_sfd(DEFAULT_SFD);
@@ -107,7 +114,7 @@ impl<'d, T: Instance> Radio<'d, T> {
 
     /// Changes the radio channel
     pub fn set_channel(&mut self, channel: u8) {
-        let r = T::regs();
+        let r = self.r;
         if channel < 11 || channel > 26 {
             panic!("Bad 802.15.4 channel");
         }
@@ -121,7 +128,7 @@ impl<'d, T: Instance> Radio<'d, T> {
 
     /// Changes the Clear Channel Assessment method
     pub fn set_cca(&mut self, cca: Cca) {
-        let r = T::regs();
+        let r = self.r;
         self.needs_enable = true;
         match cca {
             Cca::CarrierSense => r.ccactrl().write(|w| w.set_ccamode(vals::Ccamode::CARRIER_MODE)),
@@ -138,19 +145,19 @@ impl<'d, T: Instance> Radio<'d, T> {
 
     /// Changes the Start of Frame Delimiter (SFD)
     pub fn set_sfd(&mut self, sfd: u8) {
-        let r = T::regs();
+        let r = self.r;
         r.sfd().write(|w| w.set_sfd(sfd));
     }
 
     /// Clear interrupts
     pub fn clear_all_interrupts(&mut self) {
-        let r = T::regs();
+        let r = self.r;
         r.intenclr().write(|w| w.0 = 0xffff_ffff);
     }
 
     /// Changes the radio transmission power
     pub fn set_transmission_power(&mut self, power: i8) {
-        let r = T::regs();
+        let r = self.r;
         self.needs_enable = true;
 
         let tx_power: TxPower = match power {
@@ -201,12 +208,12 @@ impl<'d, T: Instance> Radio<'d, T> {
 
     /// Get the current radio state
     fn state(&self) -> RadioState {
-        T::regs().state().read().state()
+        self.r.state().read().state()
     }
 
     /// Moves the radio from any state to the DISABLED state
     fn disable(&mut self) {
-        let r = T::regs();
+        let r = self.r;
         // See figure 110 in nRF52840-PS
         loop {
             match self.state() {
@@ -238,15 +245,15 @@ impl<'d, T: Instance> Radio<'d, T> {
     }
 
     fn set_buffer(&mut self, buffer: &[u8]) {
-        let r = T::regs();
+        let r = self.r;
         r.packetptr().write_value(buffer.as_ptr() as u32);
     }
 
     /// Moves the radio to the RXIDLE state
     fn receive_prepare(&mut self) {
         // clear related events
-        T::regs().events_ccabusy().write_value(0);
-        T::regs().events_phyend().write_value(0);
+        self.r.events_ccabusy().write_value(0);
+        self.r.events_phyend().write_value(0);
         // NOTE to avoid errata 204 (see rev1 v1.4) we do TX_IDLE -> DISABLED -> RXIDLE
         let disable = match self.state() {
             RadioState::DISABLED => false,
@@ -263,7 +270,7 @@ impl<'d, T: Instance> Radio<'d, T> {
     fn receive_start(&mut self, packet: &mut Packet) {
         // NOTE we do NOT check the address of `packet` because the mutable reference ensures it's
         // allocated in RAM
-        let r = T::regs();
+        let r = self.r;
 
         self.receive_prepare();
 
@@ -290,7 +297,7 @@ impl<'d, T: Instance> Radio<'d, T> {
 
     /// Cancel receiving packet
     fn receive_cancel() {
-        let r = T::regs();
+        let r = crate::pac::RADIO;
         r.shorts().write(|_| {});
         r.tasks_stop().write_value(1);
         loop {
@@ -309,8 +316,8 @@ impl<'d, T: Instance> Radio<'d, T> {
     /// validated by the hardware; otherwise it returns the `Err` variant. In either case, `packet`
     /// will be updated with the received packet's data
     pub async fn receive(&mut self, packet: &mut Packet) -> Result<(), Error> {
-        let s = T::state();
-        let r = T::regs();
+        let s = self.state;
+        let r = self.r;
 
         // Start the read
         self.receive_start(packet);
@@ -356,8 +363,8 @@ impl<'d, T: Instance> Radio<'d, T> {
     // NOTE we do NOT check the address of `packet` because the mutable reference ensures it's
     // allocated in RAM
     pub async fn try_send(&mut self, packet: &mut Packet) -> Result<(), Error> {
-        let s = T::state();
-        let r = T::regs();
+        let s = self.state;
+        let r = self.r;
 
         // enable radio to perform cca
         self.receive_prepare();
@@ -535,3 +542,19 @@ fn dma_start_fence() {
 fn dma_end_fence() {
     compiler_fence(Ordering::Acquire);
 }
+
+mod errata {
+    pub fn post_power() {
+        // Workaround for anomaly 158
+        #[cfg(feature = "_nrf5340-net")]
+        for i in 0..32 {
+            let info = crate::pac::FICR.trimcnf(i);
+            let addr = info.addr().read();
+            if addr & 0xFFFF_F000 == crate::pac::RADIO.as_ptr() as u32 {
+                unsafe {
+                    (addr as *mut u32).write_volatile(info.data().read());
+                }
+            }
+        }
+    }
+}
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index 9d3130e6e..8070c1afe 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -56,21 +56,23 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 /// A wrapper around an nRF RNG peripheral.
 ///
 /// It has a non-blocking API, and a blocking api through `rand`.
-pub struct Rng<'d, T: Instance, M: Mode> {
-    _peri: Peri<'d, T>,
-    _phantom: PhantomData<M>,
+pub struct Rng<'d, M: Mode> {
+    r: pac::rng::Rng,
+    state: &'static State,
+    _phantom: PhantomData<(&'d (), M)>,
 }
 
-impl<'d, T: Instance> Rng<'d, T, Blocking> {
+impl<'d> Rng<'d, Blocking> {
     /// Creates a new RNG driver from the `RNG` peripheral and interrupt.
     ///
     /// SAFETY: The future returned from `fill_bytes` must not have its lifetime end without running its destructor,
     /// e.g. using `mem::forget`.
     ///
     /// The synchronous API is safe.
-    pub fn new_blocking(rng: Peri<'d, T>) -> Self {
+    pub fn new_blocking<T: Instance>(_rng: Peri<'d, T>) -> Self {
         let this = Self {
-            _peri: rng,
+            r: T::regs(),
+            state: T::state(),
             _phantom: PhantomData,
         };
 
@@ -80,19 +82,20 @@ impl<'d, T: Instance> Rng<'d, T, Blocking> {
     }
 }
 
-impl<'d, T: Instance> Rng<'d, T, Async> {
+impl<'d> Rng<'d, Async> {
     /// Creates a new RNG driver from the `RNG` peripheral and interrupt.
     ///
     /// SAFETY: The future returned from `fill_bytes` must not have its lifetime end without running its destructor,
     /// e.g. using `mem::forget`.
     ///
     /// The synchronous API is safe.
-    pub fn new(
-        rng: Peri<'d, T>,
+    pub fn new<T: Instance>(
+        _rng: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
         let this = Self {
-            _peri: rng,
+            r: T::regs(),
+            state: T::state(),
             _phantom: PhantomData,
         };
 
@@ -106,11 +109,11 @@ impl<'d, T: Instance> Rng<'d, T, Async> {
     }
 
     fn enable_irq(&self) {
-        T::regs().intenset().write(|w| w.set_valrdy(true));
+        self.r.intenset().write(|w| w.set_valrdy(true));
     }
 
     fn disable_irq(&self) {
-        T::regs().intenclr().write(|w| w.set_valrdy(true));
+        self.r.intenclr().write(|w| w.set_valrdy(true));
     }
 
     /// Fill the buffer with random bytes.
@@ -120,10 +123,11 @@ impl<'d, T: Instance> Rng<'d, T, Async> {
         }
 
         let range = dest.as_mut_ptr_range();
+        let state = self.state;
         // Even if we've preempted the interrupt, it can't preempt us again,
         // so we don't need to worry about the order we write these in.
         critical_section::with(|cs| {
-            let mut state = T::state().borrow_mut(cs);
+            let mut state = state.borrow_mut(cs);
             state.ptr = range.start;
             state.end = range.end;
         });
@@ -136,7 +140,7 @@ impl<'d, T: Instance> Rng<'d, T, Async> {
             self.disable_irq();
 
             critical_section::with(|cs| {
-                let mut state = T::state().borrow_mut(cs);
+                let mut state = state.borrow_mut(cs);
                 state.ptr = ptr::null_mut();
                 state.end = ptr::null_mut();
             });
@@ -144,7 +148,7 @@ impl<'d, T: Instance> Rng<'d, T, Async> {
 
         poll_fn(|cx| {
             critical_section::with(|cs| {
-                let mut s = T::state().borrow_mut(cs);
+                let mut s = state.borrow_mut(cs);
                 s.waker.register(cx.waker());
                 if s.ptr == s.end {
                     // We're done.
@@ -161,13 +165,13 @@ impl<'d, T: Instance> Rng<'d, T, Async> {
     }
 }
 
-impl<'d, T: Instance, M: Mode> Rng<'d, T, M> {
+impl<'d, M: Mode> Rng<'d, M> {
     fn stop(&self) {
-        T::regs().tasks_stop().write_value(1)
+        self.r.tasks_stop().write_value(1)
     }
 
     fn start(&self) {
-        T::regs().tasks_start().write_value(1)
+        self.r.tasks_start().write_value(1)
     }
 
     /// Enable or disable the RNG's bias correction.
@@ -177,7 +181,7 @@ impl<'d, T: Instance, M: Mode> Rng<'d, T, M> {
     ///
     /// Defaults to disabled.
     pub fn set_bias_correction(&self, enable: bool) {
-        T::regs().config().write(|w| w.set_dercen(enable))
+        self.r.config().write(|w| w.set_dercen(enable))
     }
 
     /// Fill the buffer with random bytes, blocking version.
@@ -185,7 +189,7 @@ impl<'d, T: Instance, M: Mode> Rng<'d, T, M> {
         self.start();
 
         for byte in dest.iter_mut() {
-            let regs = T::regs();
+            let regs = self.r;
             while regs.events_valrdy().read() == 0 {}
             regs.events_valrdy().write_value(0);
             *byte = regs.value().read().value();
@@ -210,18 +214,18 @@ impl<'d, T: Instance, M: Mode> Rng<'d, T, M> {
     }
 }
 
-impl<'d, T: Instance, M: Mode> Drop for Rng<'d, T, M> {
+impl<'d, M: Mode> Drop for Rng<'d, M> {
     fn drop(&mut self) {
         self.stop();
         critical_section::with(|cs| {
-            let mut state = T::state().borrow_mut(cs);
+            let mut state = self.state.borrow_mut(cs);
             state.ptr = ptr::null_mut();
             state.end = ptr::null_mut();
         });
     }
 }
 
-impl<'d, T: Instance, M: Mode> rand_core_06::RngCore for Rng<'d, T, M> {
+impl<'d, M: Mode> rand_core_06::RngCore for Rng<'d, M> {
     fn fill_bytes(&mut self, dest: &mut [u8]) {
         self.blocking_fill_bytes(dest);
     }
@@ -237,9 +241,9 @@ impl<'d, T: Instance, M: Mode> rand_core_06::RngCore for Rng<'d, T, M> {
     }
 }
 
-impl<'d, T: Instance, M: Mode> rand_core_06::CryptoRng for Rng<'d, T, M> {}
+impl<'d, M: Mode> rand_core_06::CryptoRng for Rng<'d, M> {}
 
-impl<'d, T: Instance, M: Mode> rand_core_09::RngCore for Rng<'d, T, M> {
+impl<'d, M: Mode> rand_core_09::RngCore for Rng<'d, M> {
     fn fill_bytes(&mut self, dest: &mut [u8]) {
         self.blocking_fill_bytes(dest);
     }
@@ -251,7 +255,7 @@ impl<'d, T: Instance, M: Mode> rand_core_09::RngCore for Rng<'d, T, M> {
     }
 }
 
-impl<'d, T: Instance, M: Mode> rand_core_09::CryptoRng for Rng<'d, T, M> {}
+impl<'d, M: Mode> rand_core_09::CryptoRng for Rng<'d, M> {}
 
 /// Peripheral static state
 pub(crate) struct State {
diff --git a/embassy-nrf/src/rramc.rs b/embassy-nrf/src/rramc.rs
index 7cb5660cb..521ac4ee7 100644
--- a/embassy-nrf/src/rramc.rs
+++ b/embassy-nrf/src/rramc.rs
@@ -7,7 +7,7 @@ use embedded_storage::nor_flash::{
 };
 
 use crate::peripherals::RRAMC;
-use crate::{pac, Peri};
+use crate::{Peri, pac};
 
 //
 // Export Nvmc alias and page size for downstream compatibility
diff --git a/embassy-nrf/src/rtc.rs b/embassy-nrf/src/rtc.rs
index 1a90d1e24..652de511b 100644
--- a/embassy-nrf/src/rtc.rs
+++ b/embassy-nrf/src/rtc.rs
@@ -2,10 +2,13 @@
 
 #![macro_use]
 
+use core::marker::PhantomData;
+
+use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_hal_internal::{Peri, PeripheralType};
 
-use crate::chip::interrupt::typelevel::Interrupt as _;
-use crate::pac;
+use crate::interrupt::typelevel::Interrupt as _;
+use crate::{interrupt, pac};
 
 /// Prescaler has an invalid value which exceeds 12 bits.
 #[derive(Debug, PartialEq, Eq)]
@@ -88,23 +91,31 @@ macro_rules! impl_rtc {
 }
 
 /// nRF RTC driver.
-pub struct Rtc<'d, T: Instance>(Peri<'d, T>);
+pub struct Rtc<'d> {
+    r: pac::rtc::Rtc,
+    irq: interrupt::Interrupt,
+    _phantom: PhantomData<&'d ()>,
+}
 
-impl<'d, T: Instance> Rtc<'d, T> {
+impl<'d> Rtc<'d> {
     /// Create a new `Rtc` driver.
     ///
     /// fRTC \[Hz\] = 32_768 / (`prescaler` + 1 )
-    pub fn new(rtc: Peri<'d, T>, prescaler: u32) -> Result<Self, PrescalerOutOfRangeError> {
+    pub fn new<T: Instance>(_rtc: Peri<'d, T>, prescaler: u32) -> Result<Self, PrescalerOutOfRangeError> {
         if prescaler >= (1 << 12) {
             return Err(PrescalerOutOfRangeError(prescaler));
         }
 
         T::regs().prescaler().write(|w| w.set_prescaler(prescaler as u16));
-        Ok(Self(rtc))
+        Ok(Self {
+            r: T::regs(),
+            irq: T::Interrupt::IRQ,
+            _phantom: PhantomData,
+        })
     }
 
     /// Create a new `Rtc` driver, configuring it to run at the given frequency.
-    pub fn new_for_freq(rtc: Peri<'d, T>, freq_hz: u32) -> Result<Self, PrescalerOutOfRangeError> {
+    pub fn new_for_freq<T: Instance>(rtc: Peri<'d, T>, freq_hz: u32) -> Result<Self, PrescalerOutOfRangeError> {
         let prescaler = (32_768 / freq_hz).saturating_sub(1);
         Self::new(rtc, prescaler)
     }
@@ -115,34 +126,38 @@ impl<'d, T: Instance> Rtc<'d, T> {
     ///
     /// Potentially allows to create multiple instances of the driver for the same peripheral
     /// which can lead to undefined behavior.
-    pub unsafe fn steal() -> Self {
-        Self(unsafe { T::steal() })
+    pub unsafe fn steal<T: Instance>() -> Self {
+        Self {
+            r: T::regs(),
+            irq: T::Interrupt::IRQ,
+            _phantom: PhantomData,
+        }
     }
 
     /// Direct access to the RTC registers.
     #[cfg(feature = "unstable-pac")]
     #[inline]
     pub fn regs(&mut self) -> pac::rtc::Rtc {
-        T::regs()
+        self.r
     }
 
     /// Enable the RTC.
     #[inline]
     pub fn enable(&mut self) {
-        T::regs().tasks_start().write_value(1);
+        self.r.tasks_start().write_value(1);
     }
 
     /// Disable the RTC.
     #[inline]
     pub fn disable(&mut self) {
-        T::regs().tasks_stop().write_value(1);
+        self.r.tasks_stop().write_value(1);
     }
 
     /// Enables interrupts for the given [Interrupt] source.
     ///
     /// Optionally also enables the interrupt in the NVIC.
     pub fn enable_interrupt(&mut self, int: Interrupt, enable_in_nvic: bool) {
-        let regs = T::regs();
+        let regs = self.r;
         match int {
             Interrupt::Tick => regs.intenset().write(|w| w.set_tick(true)),
             Interrupt::Overflow => regs.intenset().write(|w| w.set_ovrflw(true)),
@@ -152,7 +167,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
             Interrupt::Compare3 => regs.intenset().write(|w| w.set_compare(3, true)),
         }
         if enable_in_nvic {
-            unsafe { T::Interrupt::enable() };
+            unsafe { self.irq.enable() };
         }
     }
 
@@ -160,7 +175,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
     ///
     /// Optionally also disables the interrupt in the NVIC.
     pub fn disable_interrupt(&mut self, int: Interrupt, disable_in_nvic: bool) {
-        let regs = T::regs();
+        let regs = self.r;
         match int {
             Interrupt::Tick => regs.intenclr().write(|w| w.set_tick(true)),
             Interrupt::Overflow => regs.intenclr().write(|w| w.set_ovrflw(true)),
@@ -170,13 +185,13 @@ impl<'d, T: Instance> Rtc<'d, T> {
             Interrupt::Compare3 => regs.intenclr().write(|w| w.set_compare(3, true)),
         }
         if disable_in_nvic {
-            T::Interrupt::disable();
+            self.irq.disable();
         }
     }
 
     /// Enable the generation of a hardware event from a given stimulus.
     pub fn enable_event(&mut self, evt: Interrupt) {
-        let regs = T::regs();
+        let regs = self.r;
         match evt {
             Interrupt::Tick => regs.evtenset().write(|w| w.set_tick(true)),
             Interrupt::Overflow => regs.evtenset().write(|w| w.set_ovrflw(true)),
@@ -189,7 +204,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
 
     /// Disable the generation of a hardware event from a given stimulus.
     pub fn disable_event(&mut self, evt: Interrupt) {
-        let regs = T::regs();
+        let regs = self.r;
         match evt {
             Interrupt::Tick => regs.evtenclr().write(|w| w.set_tick(true)),
             Interrupt::Overflow => regs.evtenclr().write(|w| w.set_ovrflw(true)),
@@ -202,7 +217,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
 
     /// Resets the given event.
     pub fn reset_event(&mut self, evt: Interrupt) {
-        let regs = T::regs();
+        let regs = self.r;
         match evt {
             Interrupt::Tick => regs.events_tick().write_value(0),
             Interrupt::Overflow => regs.events_ovrflw().write_value(0),
@@ -215,7 +230,7 @@ impl<'d, T: Instance> Rtc<'d, T> {
 
     /// Checks if the given event has been triggered.
     pub fn is_event_triggered(&self, evt: Interrupt) -> bool {
-        let regs = T::regs();
+        let regs = self.r;
         let val = match evt {
             Interrupt::Tick => regs.events_tick().read(),
             Interrupt::Overflow => regs.events_ovrflw().read(),
@@ -241,25 +256,19 @@ impl<'d, T: Instance> Rtc<'d, T> {
             CompareChannel::_3 => 3,
         };
 
-        T::regs().cc(reg).write(|w| w.set_compare(val));
+        self.r.cc(reg).write(|w| w.set_compare(val));
         Ok(())
     }
 
     /// Clear the Real Time Counter.
     #[inline]
     pub fn clear(&self) {
-        T::regs().tasks_clear().write_value(1);
+        self.r.tasks_clear().write_value(1);
     }
 
     /// Obtain the current value of the Real Time Counter, 24 bits of range.
     #[inline]
     pub fn read(&self) -> u32 {
-        T::regs().counter().read().counter()
-    }
-
-    /// Relase the RTC, returning the underlying peripheral instance.
-    #[inline]
-    pub fn release(self) -> Peri<'d, T> {
-        self.0
+        self.r.counter().read().counter()
     }
 }
diff --git a/embassy-nrf/src/saadc.rs b/embassy-nrf/src/saadc.rs
index 92b6fb01f..a199c1c4d 100644
--- a/embassy-nrf/src/saadc.rs
+++ b/embassy-nrf/src/saadc.rs
@@ -4,11 +4,11 @@
 
 use core::future::poll_fn;
 use core::marker::PhantomData;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::{impl_peripheral, Peri};
+use embassy_hal_internal::{Peri, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
 pub(crate) use vals::Psel as InputChannel;
 
@@ -457,6 +457,19 @@ impl<'d> Saadc<'d, 1> {
 
 impl<'d, const N: usize> Drop for Saadc<'d, N> {
     fn drop(&mut self) {
+        // Reset of SAADC.
+        //
+        // This is needed when more than one pin is sampled to avoid needless power consumption.
+        // More information can be found in [nrf52 Anomaly 241](https://docs.nordicsemi.com/bundle/errata_nRF52810_Rev1/page/ERR/nRF52810/Rev1/latest/anomaly_810_241.html).
+        // The workaround seems like it copies the configuration before reset and reapplies it after.
+        // The instance is dropped, forcing a reconfiguration at compile time, hence we only
+        // call what is the reset portion of the workaround.
+        #[cfg(feature = "_nrf52")]
+        {
+            unsafe { core::ptr::write_volatile(0x40007FFC as *mut u32, 0) }
+            unsafe { core::ptr::read_volatile(0x40007FFC as *const ()) }
+            unsafe { core::ptr::write_volatile(0x40007FFC as *mut u32, 1) }
+        }
         let r = Self::regs();
         r.enable().write(|w| w.set_enable(false));
         for i in 0..N {
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index c410e49fd..ce994dbc9 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -6,17 +6,17 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 #[cfg(feature = "_nrf52832_anomaly_109")]
 use core::sync::atomic::AtomicU8;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
-pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+pub use embedded_hal_02::spi::{MODE_0, MODE_1, MODE_2, MODE_3, Mode, Phase, Polarity};
 pub use pac::spim::vals::{Frequency, Order as BitOrder};
 
 use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
-use crate::gpio::{self, convert_drive, AnyPin, OutputDrive, Pin as GpioPin, PselBits, SealedPin as _};
+use crate::gpio::{self, AnyPin, OutputDrive, Pin as GpioPin, PselBits, SealedPin as _, convert_drive};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::gpio::vals as gpiovals;
 use crate::pac::spim::vals;
diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 2a3928d25..885821146 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -3,17 +3,17 @@
 #![macro_use]
 use core::future::poll_fn;
 use core::marker::PhantomData;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
-pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+pub use embedded_hal_02::spi::{MODE_0, MODE_1, MODE_2, MODE_3, Mode, Phase, Polarity};
 pub use pac::spis::vals::Order as BitOrder;
 
 use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
-use crate::gpio::{self, convert_drive, AnyPin, OutputDrive, Pin as GpioPin, SealedPin as _};
+use crate::gpio::{self, AnyPin, OutputDrive, Pin as GpioPin, SealedPin as _, convert_drive};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::gpio::vals as gpiovals;
 use crate::pac::spis::vals;
@@ -96,14 +96,16 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
     }
 }
 
-/// SPIS driver.
-pub struct Spis<'d, T: Instance> {
-    _p: Peri<'d, T>,
+/// Serial Peripheral Interface in slave mode.
+pub struct Spis<'d> {
+    r: pac::spis::Spis,
+    state: &'static State,
+    _p: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Spis<'d, T> {
+impl<'d> Spis<'d> {
     /// Create a new SPIS driver.
-    pub fn new(
+    pub fn new<T: Instance>(
         spis: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         cs: Peri<'d, impl GpioPin>,
@@ -123,7 +125,7 @@ impl<'d, T: Instance> Spis<'d, T> {
     }
 
     /// Create a new SPIS driver, capable of TX only (MISO only).
-    pub fn new_txonly(
+    pub fn new_txonly<T: Instance>(
         spis: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         cs: Peri<'d, impl GpioPin>,
@@ -135,7 +137,7 @@ impl<'d, T: Instance> Spis<'d, T> {
     }
 
     /// Create a new SPIS driver, capable of RX only (MOSI only).
-    pub fn new_rxonly(
+    pub fn new_rxonly<T: Instance>(
         spis: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         cs: Peri<'d, impl GpioPin>,
@@ -147,7 +149,7 @@ impl<'d, T: Instance> Spis<'d, T> {
     }
 
     /// Create a new SPIS driver, capable of TX only (MISO only) without SCK pin.
-    pub fn new_txonly_nosck(
+    pub fn new_txonly_nosck<T: Instance>(
         spis: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         cs: Peri<'d, impl GpioPin>,
@@ -157,8 +159,8 @@ impl<'d, T: Instance> Spis<'d, T> {
         Self::new_inner(spis, cs.into(), None, Some(miso.into()), None, config)
     }
 
-    fn new_inner(
-        spis: Peri<'d, T>,
+    fn new_inner<T: Instance>(
+        _spis: Peri<'d, T>,
         cs: Peri<'d, AnyPin>,
         sck: Option<Peri<'d, AnyPin>>,
         miso: Option<Peri<'d, AnyPin>>,
@@ -191,10 +193,14 @@ impl<'d, T: Instance> Spis<'d, T> {
         // Enable SPIS instance.
         r.enable().write(|w| w.set_enable(vals::Enable::ENABLED));
 
-        let mut spis = Self { _p: spis };
+        let mut spis = Self {
+            r: T::regs(),
+            state: T::state(),
+            _p: PhantomData,
+        };
 
         // Apply runtime peripheral configuration
-        Self::set_config(&mut spis, &config).unwrap();
+        spis.set_config(&config).unwrap();
 
         // Disable all events interrupts.
         r.intenclr().write(|w| w.0 = 0xFFFF_FFFF);
@@ -212,7 +218,7 @@ impl<'d, T: Instance> Spis<'d, T> {
 
         compiler_fence(Ordering::SeqCst);
 
-        let r = T::regs();
+        let r = self.r;
 
         // Set up the DMA write.
         if tx.len() > EASY_DMA_SIZE {
@@ -239,7 +245,7 @@ impl<'d, T: Instance> Spis<'d, T> {
 
     fn blocking_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(usize, usize), Error> {
         compiler_fence(Ordering::SeqCst);
-        let r = T::regs();
+        let r = self.r;
 
         // Acquire semaphore.
         if r.semstat().read().0 != 1 {
@@ -276,8 +282,8 @@ impl<'d, T: Instance> Spis<'d, T> {
     }
 
     async fn async_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(usize, usize), Error> {
-        let r = T::regs();
-        let s = T::state();
+        let r = self.r;
+        let s = self.state;
 
         // Clear status register.
         r.status().write(|w| {
@@ -420,21 +426,21 @@ impl<'d, T: Instance> Spis<'d, T> {
 
     /// Checks if last transaction overread.
     pub fn is_overread(&mut self) -> bool {
-        T::regs().status().read().overread()
+        self.r.status().read().overread()
     }
 
     /// Checks if last transaction overflowed.
     pub fn is_overflow(&mut self) -> bool {
-        T::regs().status().read().overflow()
+        self.r.status().read().overflow()
     }
 }
 
-impl<'d, T: Instance> Drop for Spis<'d, T> {
+impl<'d> Drop for Spis<'d> {
     fn drop(&mut self) {
         trace!("spis drop");
 
         // Disable
-        let r = T::regs();
+        let r = self.r;
         r.enable().write(|w| w.set_enable(vals::Enable::DISABLED));
 
         gpio::deconfigure_pin(r.psel().sck().read());
@@ -489,11 +495,11 @@ macro_rules! impl_spis {
 
 // ====================
 
-impl<'d, T: Instance> SetConfig for Spis<'d, T> {
+impl<'d> SetConfig for Spis<'d> {
     type Config = Config;
     type ConfigError = ();
     fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
-        let r = T::regs();
+        let r = self.r;
         // Configure mode.
         let mode = config.mode;
         r.config().write(|w| {
diff --git a/embassy-nrf/src/temp.rs b/embassy-nrf/src/temp.rs
index 44be0f6d1..a20e300b7 100644
--- a/embassy-nrf/src/temp.rs
+++ b/embassy-nrf/src/temp.rs
@@ -9,7 +9,7 @@ use fixed::types::I30F2;
 
 use crate::interrupt::InterruptExt;
 use crate::peripherals::TEMP;
-use crate::{interrupt, pac, Peri};
+use crate::{Peri, interrupt, pac};
 
 /// Interrupt handler.
 pub struct InterruptHandler {
diff --git a/embassy-nrf/src/time_driver.rs b/embassy-nrf/src/time_driver.rs
index 03f4c2e2b..b723e2334 100644
--- a/embassy-nrf/src/time_driver.rs
+++ b/embassy-nrf/src/time_driver.rs
@@ -1,9 +1,9 @@
 use core::cell::{Cell, RefCell};
-use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
+use core::sync::atomic::{AtomicU32, Ordering, compiler_fence};
 
 use critical_section::CriticalSection;
-use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_time_driver::Driver;
 use embassy_time_queue_utils::Queue;
 
diff --git a/embassy-nrf/src/timer.rs b/embassy-nrf/src/timer.rs
index 1d1f77ea8..0b0bb9780 100644
--- a/embassy-nrf/src/timer.rs
+++ b/embassy-nrf/src/timer.rs
@@ -6,6 +6,8 @@
 
 #![macro_use]
 
+use core::marker::PhantomData;
+
 use embassy_hal_internal::{Peri, PeripheralType};
 
 use crate::pac;
@@ -81,16 +83,18 @@ pub enum Frequency {
 ///
 /// It has either 4 or 6 Capture/Compare registers, which can be used to capture the current state of the counter
 /// or trigger an event when the counter reaches a certain value.
-pub struct Timer<'d, T: Instance> {
-    _p: Peri<'d, T>,
+pub struct Timer<'d> {
+    r: pac::timer::Timer,
+    ccs: usize,
+    _p: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Timer<'d, T> {
+impl<'d> Timer<'d> {
     /// Create a new `Timer` driver.
     ///
     /// This can be useful for triggering tasks via PPI.
     /// `Uarte` uses this internally.
-    pub fn new(timer: Peri<'d, T>) -> Self {
+    pub fn new<T: Instance>(timer: Peri<'d, T>) -> Self {
         Self::new_inner(timer, false)
     }
 
@@ -98,14 +102,18 @@ impl<'d, T: Instance> Timer<'d, T> {
     ///
     /// This can be useful for triggering tasks via PPI.
     /// `Uarte` uses this internally.
-    pub fn new_counter(timer: Peri<'d, T>) -> Self {
+    pub fn new_counter<T: Instance>(timer: Peri<'d, T>) -> Self {
         Self::new_inner(timer, true)
     }
 
-    fn new_inner(timer: Peri<'d, T>, is_counter: bool) -> Self {
+    fn new_inner<T: Instance>(_timer: Peri<'d, T>, is_counter: bool) -> Self {
         let regs = T::regs();
 
-        let this = Self { _p: timer };
+        let this = Self {
+            r: regs,
+            ccs: T::CCS,
+            _p: PhantomData,
+        };
 
         // Stop the timer before doing anything else,
         // since changing BITMODE while running can cause 'unpredictable behaviour' according to the specification.
@@ -131,7 +139,7 @@ impl<'d, T: Instance> Timer<'d, T> {
         // Default to the max frequency of the lower power clock
         this.set_frequency(Frequency::F1MHz);
 
-        for n in 0..T::CCS {
+        for n in 0..this.ccs {
             let cc = this.cc(n);
             // Initialize all the shorts as disabled.
             cc.unshort_compare_clear();
@@ -147,43 +155,43 @@ impl<'d, T: Instance> Timer<'d, T> {
     #[cfg(feature = "unstable-pac")]
     #[inline]
     pub fn regs(&mut self) -> pac::timer::Timer {
-        T::regs()
+        self.r
     }
 
     /// Starts the timer.
     pub fn start(&self) {
-        T::regs().tasks_start().write_value(1)
+        self.r.tasks_start().write_value(1)
     }
 
     /// Stops the timer.
     pub fn stop(&self) {
-        T::regs().tasks_stop().write_value(1)
+        self.r.tasks_stop().write_value(1)
     }
 
     /// Reset the timer's counter to 0.
     pub fn clear(&self) {
-        T::regs().tasks_clear().write_value(1)
+        self.r.tasks_clear().write_value(1)
     }
 
     /// Returns the START task, for use with PPI.
     ///
     /// When triggered, this task starts the timer.
     pub fn task_start(&self) -> Task<'d> {
-        Task::from_reg(T::regs().tasks_start())
+        Task::from_reg(self.r.tasks_start())
     }
 
     /// Returns the STOP task, for use with PPI.
     ///
     /// When triggered, this task stops the timer.
     pub fn task_stop(&self) -> Task<'d> {
-        Task::from_reg(T::regs().tasks_stop())
+        Task::from_reg(self.r.tasks_stop())
     }
 
     /// Returns the CLEAR task, for use with PPI.
     ///
     /// When triggered, this task resets the timer's counter to 0.
     pub fn task_clear(&self) -> Task<'d> {
-        Task::from_reg(T::regs().tasks_clear())
+        Task::from_reg(self.r.tasks_clear())
     }
 
     /// Returns the COUNT task, for use with PPI.
@@ -191,7 +199,7 @@ impl<'d, T: Instance> Timer<'d, T> {
     /// When triggered, this task increments the timer's counter by 1.
     /// Only works in counter mode.
     pub fn task_count(&self) -> Task<'d> {
-        Task::from_reg(T::regs().tasks_count())
+        Task::from_reg(self.r.tasks_count())
     }
 
     /// Change the timer's frequency.
@@ -201,7 +209,7 @@ impl<'d, T: Instance> Timer<'d, T> {
     pub fn set_frequency(&self, frequency: Frequency) {
         self.stop();
 
-        T::regs()
+        self.r
             .prescaler()
             // SAFETY: `frequency` is a variant of `Frequency`,
             // whose values are all in the range of 0-9 (the valid range of `prescaler`).
@@ -212,18 +220,19 @@ impl<'d, T: Instance> Timer<'d, T> {
     ///
     /// # Panics
     /// Panics if `n` >= the number of CC registers this timer has (4 for a normal timer, 6 for an extended timer).
-    pub fn cc(&self, n: usize) -> Cc<'d, T> {
-        if n >= T::CCS {
-            panic!("Cannot get CC register {} of timer with {} CC registers.", n, T::CCS);
+    pub fn cc(&self, n: usize) -> Cc<'d> {
+        if n >= self.ccs {
+            panic!("Cannot get CC register {} of timer with {} CC registers.", n, self.ccs);
         }
         Cc {
             n,
-            _p: unsafe { self._p.clone_unchecked() },
+            r: self.r,
+            _p: PhantomData,
         }
     }
 }
 
-impl<T: Instance> Timer<'static, T> {
+impl Timer<'static> {
     /// Persist the timer's configuration for the rest of the program's lifetime. This method
     /// should be preferred over [`core::mem::forget()`] because the `'static` bound prevents
     /// accidental reuse of the underlying peripheral.
@@ -232,7 +241,7 @@ impl<T: Instance> Timer<'static, T> {
     }
 }
 
-impl<'d, T: Instance> Drop for Timer<'d, T> {
+impl<'d> Drop for Timer<'d> {
     fn drop(&mut self) {
         self.stop();
     }
@@ -245,27 +254,28 @@ impl<'d, T: Instance> Drop for Timer<'d, T> {
 ///
 /// The timer will fire the register's COMPARE event when its counter reaches the value stored in the register.
 /// When the register's CAPTURE task is triggered, the timer will store the current value of its counter in the register
-pub struct Cc<'d, T: Instance> {
+pub struct Cc<'d> {
     n: usize,
-    _p: Peri<'d, T>,
+    r: pac::timer::Timer,
+    _p: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Cc<'d, T> {
+impl<'d> Cc<'d> {
     /// Get the current value stored in the register.
     pub fn read(&self) -> u32 {
-        T::regs().cc(self.n).read()
+        self.r.cc(self.n).read()
     }
 
     /// Set the value stored in the register.
     ///
     /// `event_compare` will fire when the timer's counter reaches this value.
     pub fn write(&self, value: u32) {
-        T::regs().cc(self.n).write_value(value);
+        self.r.cc(self.n).write_value(value);
     }
 
     /// Capture the current value of the timer's counter in this register, and return it.
     pub fn capture(&self) -> u32 {
-        T::regs().tasks_capture(self.n).write_value(1);
+        self.r.tasks_capture(self.n).write_value(1);
         self.read()
     }
 
@@ -273,20 +283,20 @@ impl<'d, T: Instance> Cc<'d, T> {
     ///
     /// When triggered, this task will capture the current value of the timer's counter in this register.
     pub fn task_capture(&self) -> Task<'d> {
-        Task::from_reg(T::regs().tasks_capture(self.n))
+        Task::from_reg(self.r.tasks_capture(self.n))
     }
 
     /// Returns this CC register's COMPARE event, for use with PPI.
     ///
     /// This event will fire when the timer's counter reaches the value in this CC register.
     pub fn event_compare(&self) -> Event<'d> {
-        Event::from_reg(T::regs().events_compare(self.n))
+        Event::from_reg(self.r.events_compare(self.n))
     }
 
     /// Clear the COMPARE event for this CC register.
     #[inline]
     pub fn clear_events(&self) {
-        T::regs().events_compare(self.n).write_value(0);
+        self.r.events_compare(self.n).write_value(0);
     }
 
     /// Enable the shortcut between this CC register's COMPARE event and the timer's CLEAR task.
@@ -295,12 +305,12 @@ impl<'d, T: Instance> Cc<'d, T> {
     ///
     /// So, when the timer's counter reaches the value stored in this register, the timer's counter will be reset to 0.
     pub fn short_compare_clear(&self) {
-        T::regs().shorts().modify(|w| w.set_compare_clear(self.n, true))
+        self.r.shorts().modify(|w| w.set_compare_clear(self.n, true))
     }
 
     /// Disable the shortcut between this CC register's COMPARE event and the timer's CLEAR task.
     pub fn unshort_compare_clear(&self) {
-        T::regs().shorts().modify(|w| w.set_compare_clear(self.n, false))
+        self.r.shorts().modify(|w| w.set_compare_clear(self.n, false))
     }
 
     /// Enable the shortcut between this CC register's COMPARE event and the timer's STOP task.
@@ -309,11 +319,11 @@ impl<'d, T: Instance> Cc<'d, T> {
     ///
     /// So, when the timer's counter reaches the value stored in this register, the timer will stop counting up.
     pub fn short_compare_stop(&self) {
-        T::regs().shorts().modify(|w| w.set_compare_stop(self.n, true))
+        self.r.shorts().modify(|w| w.set_compare_stop(self.n, true))
     }
 
     /// Disable the shortcut between this CC register's COMPARE event and the timer's STOP task.
     pub fn unshort_compare_stop(&self) {
-        T::regs().shorts().modify(|w| w.set_compare_stop(self.n, false))
+        self.r.shorts().modify(|w| w.set_compare_stop(self.n, false))
     }
 }
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs
index 3fc59a39a..93255c832 100644
--- a/embassy-nrf/src/twim.rs
+++ b/embassy-nrf/src/twim.rs
@@ -2,10 +2,10 @@
 
 #![macro_use]
 
-use core::future::{poll_fn, Future};
+use core::future::poll_fn;
 use core::marker::PhantomData;
-use core::sync::atomic::compiler_fence;
 use core::sync::atomic::Ordering::SeqCst;
+use core::sync::atomic::compiler_fence;
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
@@ -112,12 +112,14 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 }
 
 /// TWI driver.
-pub struct Twim<'d, T: Instance> {
-    _p: Peri<'d, T>,
+pub struct Twim<'d> {
+    r: pac::twim::Twim,
+    state: &'static State,
     tx_ram_buffer: &'d mut [u8],
+    _p: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Twim<'d, T> {
+impl<'d> Twim<'d> {
     /// Create a new TWI driver.
     ///
     /// `tx_ram_buffer` is required if any write operations will be performed with data that is not in RAM.
@@ -125,8 +127,8 @@ impl<'d, T: Instance> Twim<'d, T> {
     /// needs to be at least as large as the largest write operation that will be executed with a buffer
     /// that is not in RAM. If all write operations will be performed from RAM, an empty buffer (`&[]`) may
     /// be used.
-    pub fn new(
-        twim: Peri<'d, T>,
+    pub fn new<T: Instance>(
+        _twim: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         sda: Peri<'d, impl GpioPin>,
         scl: Peri<'d, impl GpioPin>,
@@ -167,8 +169,10 @@ impl<'d, T: Instance> Twim<'d, T> {
         r.enable().write(|w| w.set_enable(vals::Enable::ENABLED));
 
         let mut twim = Self {
-            _p: twim,
+            r: T::regs(),
+            state: T::state(),
             tx_ram_buffer,
+            _p: PhantomData {},
         };
 
         // Apply runtime peripheral configuration
@@ -201,7 +205,7 @@ impl<'d, T: Instance> Twim<'d, T> {
             return Err(Error::TxBufferTooLong);
         }
 
-        let r = T::regs();
+        let r = self.r;
 
         // We're giving the register a pointer to the stack. Since we're
         // waiting for the I2C transaction to end before this stack pointer
@@ -228,7 +232,7 @@ impl<'d, T: Instance> Twim<'d, T> {
             return Err(Error::RxBufferTooLong);
         }
 
-        let r = T::regs();
+        let r = self.r;
 
         // We're giving the register a pointer to the stack. Since we're
         // waiting for the I2C transaction to end before this stack pointer
@@ -250,7 +254,7 @@ impl<'d, T: Instance> Twim<'d, T> {
     }
 
     fn clear_errorsrc(&mut self) {
-        let r = T::regs();
+        let r = self.r;
         r.errorsrc().write(|w| {
             w.set_anack(true);
             w.set_dnack(true);
@@ -259,8 +263,8 @@ impl<'d, T: Instance> Twim<'d, T> {
     }
 
     /// Get Error instance, if any occurred.
-    fn check_errorsrc() -> Result<(), Error> {
-        let r = T::regs();
+    fn check_errorsrc(&mut self) -> Result<(), Error> {
+        let r = self.r;
 
         let err = r.errorsrc().read();
         if err.anack() {
@@ -276,7 +280,7 @@ impl<'d, T: Instance> Twim<'d, T> {
     }
 
     fn check_rx(&self, len: usize) -> Result<(), Error> {
-        let r = T::regs();
+        let r = self.r;
         if r.rxd().amount().read().0 != len as u32 {
             Err(Error::Receive)
         } else {
@@ -285,7 +289,7 @@ impl<'d, T: Instance> Twim<'d, T> {
     }
 
     fn check_tx(&self, len: usize) -> Result<(), Error> {
-        let r = T::regs();
+        let r = self.r;
         if r.txd().amount().read().0 != len as u32 {
             Err(Error::Transmit)
         } else {
@@ -295,7 +299,7 @@ impl<'d, T: Instance> Twim<'d, T> {
 
     /// Wait for stop or error
     fn blocking_wait(&mut self) {
-        let r = T::regs();
+        let r = self.r;
         loop {
             if r.events_suspended().read() != 0 || r.events_stopped().read() != 0 {
                 r.events_suspended().write_value(0);
@@ -312,7 +316,7 @@ impl<'d, T: Instance> Twim<'d, T> {
     /// Wait for stop or error
     #[cfg(feature = "time")]
     fn blocking_wait_timeout(&mut self, timeout: Duration) -> Result<(), Error> {
-        let r = T::regs();
+        let r = self.r;
         let deadline = Instant::now() + timeout;
         loop {
             if r.events_suspended().read() != 0 || r.events_stopped().read() != 0 {
@@ -333,10 +337,10 @@ impl<'d, T: Instance> Twim<'d, T> {
     }
 
     /// Wait for stop or error
-    fn async_wait(&mut self) -> impl Future<Output = Result<(), Error>> {
-        poll_fn(move |cx| {
-            let r = T::regs();
-            let s = T::state();
+    async fn async_wait(&mut self) -> Result<(), Error> {
+        poll_fn(|cx| {
+            let r = self.r;
+            let s = self.state;
 
             s.end_waker.register(cx.waker());
             if r.events_suspended().read() != 0 || r.events_stopped().read() != 0 {
@@ -349,15 +353,16 @@ impl<'d, T: Instance> Twim<'d, T> {
             if r.events_error().read() != 0 {
                 r.events_error().write_value(0);
                 r.tasks_stop().write_value(1);
-                if let Err(e) = Self::check_errorsrc() {
+                if let Err(e) = self.check_errorsrc() {
                     return Poll::Ready(Err(e));
                 } else {
-                    panic!("Found events_error bit without an error in errorsrc reg");
+                    return Poll::Ready(Err(Error::Timeout));
                 }
             }
 
             Poll::Pending
         })
+        .await
     }
 
     fn setup_operations(
@@ -367,7 +372,7 @@ impl<'d, T: Instance> Twim<'d, T> {
         last_op: Option<&Operation<'_>>,
         inten: bool,
     ) -> Result<usize, Error> {
-        let r = T::regs();
+        let r = self.r;
 
         compiler_fence(SeqCst);
 
@@ -511,7 +516,7 @@ impl<'d, T: Instance> Twim<'d, T> {
 
     fn check_operations(&mut self, operations: &[Operation<'_>]) -> Result<(), Error> {
         compiler_fence(SeqCst);
-        Self::check_errorsrc()?;
+        self.check_errorsrc()?;
 
         assert!(operations.len() == 1 || operations.len() == 2);
         match operations {
@@ -696,14 +701,14 @@ impl<'d, T: Instance> Twim<'d, T> {
     }
 }
 
-impl<'a, T: Instance> Drop for Twim<'a, T> {
+impl<'a> Drop for Twim<'a> {
     fn drop(&mut self) {
         trace!("twim drop");
 
         // TODO: check for abort
 
         // disable!
-        let r = T::regs();
+        let r = self.r;
         r.enable().write(|w| w.set_enable(vals::Enable::DISABLED));
 
         gpio::deconfigure_pin(r.psel().sda().read());
@@ -759,7 +764,7 @@ macro_rules! impl_twim {
 mod eh02 {
     use super::*;
 
-    impl<'a, T: Instance> embedded_hal_02::blocking::i2c::Write for Twim<'a, T> {
+    impl<'a> embedded_hal_02::blocking::i2c::Write for Twim<'a> {
         type Error = Error;
 
         fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
@@ -767,7 +772,7 @@ mod eh02 {
         }
     }
 
-    impl<'a, T: Instance> embedded_hal_02::blocking::i2c::Read for Twim<'a, T> {
+    impl<'a> embedded_hal_02::blocking::i2c::Read for Twim<'a> {
         type Error = Error;
 
         fn read(&mut self, addr: u8, bytes: &mut [u8]) -> Result<(), Error> {
@@ -775,7 +780,7 @@ mod eh02 {
         }
     }
 
-    impl<'a, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for Twim<'a, T> {
+    impl<'a> embedded_hal_02::blocking::i2c::WriteRead for Twim<'a> {
         type Error = Error;
 
         fn write_read<'w>(&mut self, addr: u8, bytes: &'w [u8], buffer: &'w mut [u8]) -> Result<(), Error> {
@@ -804,27 +809,27 @@ impl embedded_hal_1::i2c::Error for Error {
     }
 }
 
-impl<'d, T: Instance> embedded_hal_1::i2c::ErrorType for Twim<'d, T> {
+impl<'d> embedded_hal_1::i2c::ErrorType for Twim<'d> {
     type Error = Error;
 }
 
-impl<'d, T: Instance> embedded_hal_1::i2c::I2c for Twim<'d, T> {
+impl<'d> embedded_hal_1::i2c::I2c for Twim<'d> {
     fn transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> {
         self.blocking_transaction(address, operations)
     }
 }
 
-impl<'d, T: Instance> embedded_hal_async::i2c::I2c for Twim<'d, T> {
+impl<'d> embedded_hal_async::i2c::I2c for Twim<'d> {
     async fn transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> {
         self.transaction(address, operations).await
     }
 }
 
-impl<'d, T: Instance> SetConfig for Twim<'d, T> {
+impl<'d> SetConfig for Twim<'d> {
     type Config = Config;
     type ConfigError = ();
     fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
-        let r = T::regs();
+        let r = self.r;
         r.frequency().write(|w| w.set_frequency(config.frequency));
 
         Ok(())
diff --git a/embassy-nrf/src/twis.rs b/embassy-nrf/src/twis.rs
index c77d0f048..2bc0a5c13 100644
--- a/embassy-nrf/src/twis.rs
+++ b/embassy-nrf/src/twis.rs
@@ -2,10 +2,10 @@
 
 #![macro_use]
 
-use core::future::{poll_fn, Future};
+use core::future::{Future, poll_fn};
 use core::marker::PhantomData;
-use core::sync::atomic::compiler_fence;
 use core::sync::atomic::Ordering::SeqCst;
+use core::sync::atomic::compiler_fence;
 use core::task::Poll;
 
 use embassy_hal_internal::{Peri, PeripheralType};
@@ -140,14 +140,16 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 }
 
 /// TWIS driver.
-pub struct Twis<'d, T: Instance> {
-    _p: Peri<'d, T>,
+pub struct Twis<'d> {
+    r: pac::twis::Twis,
+    state: &'static State,
+    _p: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Twis<'d, T> {
+impl<'d> Twis<'d> {
     /// Create a new TWIS driver.
-    pub fn new(
-        twis: Peri<'d, T>,
+    pub fn new<T: Instance>(
+        _twis: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         sda: Peri<'d, impl GpioPin>,
         scl: Peri<'d, impl GpioPin>,
@@ -206,7 +208,11 @@ impl<'d, T: Instance> Twis<'d, T> {
         T::Interrupt::unpend();
         unsafe { T::Interrupt::enable() };
 
-        Self { _p: twis }
+        Self {
+            r: T::regs(),
+            state: T::state(),
+            _p: PhantomData,
+        }
     }
 
     /// Set TX buffer, checking that it is in RAM and has suitable length.
@@ -217,7 +223,7 @@ impl<'d, T: Instance> Twis<'d, T> {
             return Err(Error::TxBufferTooLong);
         }
 
-        let r = T::regs();
+        let r = self.r;
 
         // We're giving the register a pointer to the stack. Since we're
         // waiting for the I2C transaction to end before this stack pointer
@@ -244,7 +250,7 @@ impl<'d, T: Instance> Twis<'d, T> {
             return Err(Error::RxBufferTooLong);
         }
 
-        let r = T::regs();
+        let r = self.r;
 
         // We're giving the register a pointer to the stack. Since we're
         // waiting for the I2C transaction to end before this stack pointer
@@ -266,7 +272,7 @@ impl<'d, T: Instance> Twis<'d, T> {
     }
 
     fn clear_errorsrc(&mut self) {
-        let r = T::regs();
+        let r = self.r;
         r.errorsrc().write(|w| {
             w.set_overflow(true);
             w.set_overread(true);
@@ -276,18 +282,18 @@ impl<'d, T: Instance> Twis<'d, T> {
 
     /// Returns matched address for latest command.
     pub fn address_match(&self) -> u8 {
-        let r = T::regs();
+        let r = self.r;
         r.address(r.match_().read().0 as usize).read().address()
     }
 
     /// Returns the index of the address matched in the latest command.
     pub fn address_match_index(&self) -> usize {
-        T::regs().match_().read().0 as _
+        self.r.match_().read().0 as _
     }
 
     /// Wait for read, write, stop or error
     fn blocking_listen_wait(&mut self) -> Result<Status, Error> {
-        let r = T::regs();
+        let r = self.r;
         loop {
             if r.events_error().read() != 0 {
                 r.events_error().write_value(0);
@@ -312,7 +318,7 @@ impl<'d, T: Instance> Twis<'d, T> {
 
     /// Wait for stop, repeated start or error
     fn blocking_listen_wait_end(&mut self, status: Status) -> Result<Command, Error> {
-        let r = T::regs();
+        let r = self.r;
         loop {
             // stop if an error occurred
             if r.events_error().read() != 0 {
@@ -338,7 +344,7 @@ impl<'d, T: Instance> Twis<'d, T> {
 
     /// Wait for stop or error
     fn blocking_wait(&mut self) -> Result<usize, Error> {
-        let r = T::regs();
+        let r = self.r;
         loop {
             // stop if an error occurred
             if r.events_error().read() != 0 {
@@ -363,7 +369,7 @@ impl<'d, T: Instance> Twis<'d, T> {
     /// Wait for stop or error with timeout
     #[cfg(feature = "time")]
     fn blocking_wait_timeout(&mut self, timeout: Duration) -> Result<usize, Error> {
-        let r = T::regs();
+        let r = self.r;
         let deadline = Instant::now() + timeout;
         loop {
             // stop if an error occurred
@@ -392,7 +398,7 @@ impl<'d, T: Instance> Twis<'d, T> {
     /// Wait for read, write, stop or error with timeout
     #[cfg(feature = "time")]
     fn blocking_listen_wait_timeout(&mut self, timeout: Duration) -> Result<Status, Error> {
-        let r = T::regs();
+        let r = self.r;
         let deadline = Instant::now() + timeout;
         loop {
             if r.events_error().read() != 0 {
@@ -423,7 +429,7 @@ impl<'d, T: Instance> Twis<'d, T> {
     /// Wait for stop, repeated start or error with timeout
     #[cfg(feature = "time")]
     fn blocking_listen_wait_end_timeout(&mut self, status: Status, timeout: Duration) -> Result<Command, Error> {
-        let r = T::regs();
+        let r = self.r;
         let deadline = Instant::now() + timeout;
         loop {
             // stop if an error occurred
@@ -453,10 +459,9 @@ impl<'d, T: Instance> Twis<'d, T> {
 
     /// Wait for stop or error
     fn async_wait(&mut self) -> impl Future<Output = Result<usize, Error>> {
+        let r = self.r;
+        let s = self.state;
         poll_fn(move |cx| {
-            let r = T::regs();
-            let s = T::state();
-
             s.waker.register(cx.waker());
 
             // stop if an error occurred
@@ -483,10 +488,9 @@ impl<'d, T: Instance> Twis<'d, T> {
 
     /// Wait for read or write
     fn async_listen_wait(&mut self) -> impl Future<Output = Result<Status, Error>> {
+        let r = self.r;
+        let s = self.state;
         poll_fn(move |cx| {
-            let r = T::regs();
-            let s = T::state();
-
             s.waker.register(cx.waker());
 
             // stop if an error occurred
@@ -510,10 +514,9 @@ impl<'d, T: Instance> Twis<'d, T> {
 
     /// Wait for stop, repeated start or error
     fn async_listen_wait_end(&mut self, status: Status) -> impl Future<Output = Result<Command, Error>> {
+        let r = self.r;
+        let s = self.state;
         poll_fn(move |cx| {
-            let r = T::regs();
-            let s = T::state();
-
             s.waker.register(cx.waker());
 
             // stop if an error occurred
@@ -540,7 +543,7 @@ impl<'d, T: Instance> Twis<'d, T> {
     }
 
     fn setup_respond_from_ram(&mut self, buffer: &[u8], inten: bool) -> Result<(), Error> {
-        let r = T::regs();
+        let r = self.r;
 
         compiler_fence(SeqCst);
 
@@ -584,7 +587,7 @@ impl<'d, T: Instance> Twis<'d, T> {
     }
 
     fn setup_listen(&mut self, buffer: &mut [u8], inten: bool) -> Result<(), Error> {
-        let r = T::regs();
+        let r = self.r;
         compiler_fence(SeqCst);
 
         // Set up the DMA read.
@@ -620,7 +623,7 @@ impl<'d, T: Instance> Twis<'d, T> {
     }
 
     fn setup_listen_end(&mut self, inten: bool) -> Result<(), Error> {
-        let r = T::regs();
+        let r = self.r;
         compiler_fence(SeqCst);
 
         // Clear events
@@ -753,14 +756,14 @@ impl<'d, T: Instance> Twis<'d, T> {
     }
 }
 
-impl<'a, T: Instance> Drop for Twis<'a, T> {
+impl<'a> Drop for Twis<'a> {
     fn drop(&mut self) {
         trace!("twis drop");
 
         // TODO: check for abort
 
         // disable!
-        let r = T::regs();
+        let r = self.r;
         r.enable().write(|w| w.set_enable(vals::Enable::DISABLED));
 
         gpio::deconfigure_pin(r.psel().sda().read());
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 927a0ac08..1ee452173 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -15,7 +15,7 @@
 
 use core::future::poll_fn;
 use core::marker::PhantomData;
-use core::sync::atomic::{compiler_fence, AtomicU8, Ordering};
+use core::sync::atomic::{AtomicU8, Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_hal_internal::drop::OnDrop;
@@ -25,7 +25,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 pub use pac::uarte::vals::{Baudrate, ConfigParity as Parity};
 
 use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
-use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits, SealedPin as _, DISCONNECTED};
+use crate::gpio::{self, AnyPin, DISCONNECTED, Pin as GpioPin, PselBits, SealedPin as _};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::gpio::vals as gpiovals;
 use crate::pac::uarte::vals;
@@ -132,28 +132,32 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 }
 
 /// UARTE driver.
-pub struct Uarte<'d, T: Instance> {
-    tx: UarteTx<'d, T>,
-    rx: UarteRx<'d, T>,
+pub struct Uarte<'d> {
+    tx: UarteTx<'d>,
+    rx: UarteRx<'d>,
 }
 
 /// Transmitter part of the UARTE driver.
 ///
 /// This can be obtained via [`Uarte::split`], or created directly.
-pub struct UarteTx<'d, T: Instance> {
-    _p: Peri<'d, T>,
+pub struct UarteTx<'d> {
+    r: pac::uarte::Uarte,
+    state: &'static State,
+    _p: PhantomData<&'d ()>,
 }
 
 /// Receiver part of the UARTE driver.
 ///
 /// This can be obtained via [`Uarte::split`], or created directly.
-pub struct UarteRx<'d, T: Instance> {
-    _p: Peri<'d, T>,
+pub struct UarteRx<'d> {
+    r: pac::uarte::Uarte,
+    state: &'static State,
+    _p: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> Uarte<'d, T> {
+impl<'d> Uarte<'d> {
     /// Create a new UARTE without hardware flow control
-    pub fn new(
+    pub fn new<T: Instance>(
         uarte: Peri<'d, T>,
         rxd: Peri<'d, impl GpioPin>,
         txd: Peri<'d, impl GpioPin>,
@@ -164,7 +168,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
     }
 
     /// Create a new UARTE with hardware flow control (RTS/CTS)
-    pub fn new_with_rtscts(
+    pub fn new_with_rtscts<T: Instance>(
         uarte: Peri<'d, T>,
         rxd: Peri<'d, impl GpioPin>,
         txd: Peri<'d, impl GpioPin>,
@@ -183,8 +187,8 @@ impl<'d, T: Instance> Uarte<'d, T> {
         )
     }
 
-    fn new_inner(
-        uarte: Peri<'d, T>,
+    fn new_inner<T: Instance>(
+        _uarte: Peri<'d, T>,
         rxd: Peri<'d, AnyPin>,
         txd: Peri<'d, AnyPin>,
         cts: Option<Peri<'d, AnyPin>>,
@@ -211,16 +215,22 @@ impl<'d, T: Instance> Uarte<'d, T> {
 
         Self {
             tx: UarteTx {
-                _p: unsafe { uarte.clone_unchecked() },
+                r: T::regs(),
+                state: T::state(),
+                _p: PhantomData {},
+            },
+            rx: UarteRx {
+                r: T::regs(),
+                state: T::state(),
+                _p: PhantomData {},
             },
-            rx: UarteRx { _p: uarte },
         }
     }
 
     /// Split the Uarte into the transmitter and receiver parts.
     ///
     /// This is useful to concurrently transmit and receive from independent tasks.
-    pub fn split(self) -> (UarteTx<'d, T>, UarteRx<'d, T>) {
+    pub fn split(self) -> (UarteTx<'d>, UarteRx<'d>) {
         (self.tx, self.rx)
     }
 
@@ -228,7 +238,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
     ///
     /// The returned halves borrow from `self`, so you can drop them and go back to using
     /// the "un-split" `self`. This allows temporarily splitting the UART.
-    pub fn split_by_ref(&mut self) -> (&mut UarteTx<'d, T>, &mut UarteRx<'d, T>) {
+    pub fn split_by_ref(&mut self) -> (&mut UarteTx<'d>, &mut UarteRx<'d>) {
         (&mut self.tx, &mut self.rx)
     }
 
@@ -240,13 +250,13 @@ impl<'d, T: Instance> Uarte<'d, T> {
         timer: Peri<'d, U>,
         ppi_ch1: Peri<'d, impl ConfigurableChannel + 'd>,
         ppi_ch2: Peri<'d, impl ConfigurableChannel + 'd>,
-    ) -> (UarteTx<'d, T>, UarteRxWithIdle<'d, T, U>) {
+    ) -> (UarteTx<'d>, UarteRxWithIdle<'d>) {
         (self.tx, self.rx.with_idle(timer, ppi_ch1, ppi_ch2))
     }
 
     /// Return the endtx event for use with PPI
     pub fn event_endtx(&self) -> Event<'_> {
-        let r = T::regs();
+        let r = self.tx.r;
         Event::from_reg(r.events_endtx())
     }
 
@@ -343,9 +353,9 @@ pub(crate) fn configure(r: pac::uarte::Uarte, config: Config, hardware_flow_cont
     apply_workaround_for_enable_anomaly(r);
 }
 
-impl<'d, T: Instance> UarteTx<'d, T> {
+impl<'d> UarteTx<'d> {
     /// Create a new tx-only UARTE without hardware flow control
-    pub fn new(
+    pub fn new<T: Instance>(
         uarte: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         txd: Peri<'d, impl GpioPin>,
@@ -355,7 +365,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
     }
 
     /// Create a new tx-only UARTE with hardware flow control (RTS/CTS)
-    pub fn new_with_rtscts(
+    pub fn new_with_rtscts<T: Instance>(
         uarte: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         txd: Peri<'d, impl GpioPin>,
@@ -365,7 +375,12 @@ impl<'d, T: Instance> UarteTx<'d, T> {
         Self::new_inner(uarte, txd.into(), Some(cts.into()), config)
     }
 
-    fn new_inner(uarte: Peri<'d, T>, txd: Peri<'d, AnyPin>, cts: Option<Peri<'d, AnyPin>>, config: Config) -> Self {
+    fn new_inner<T: Instance>(
+        _uarte: Peri<'d, T>,
+        txd: Peri<'d, AnyPin>,
+        cts: Option<Peri<'d, AnyPin>>,
+        config: Config,
+    ) -> Self {
         let r = T::regs();
 
         configure(r, config, cts.is_some());
@@ -378,7 +393,11 @@ impl<'d, T: Instance> UarteTx<'d, T> {
         let s = T::state();
         s.tx_rx_refcount.store(1, Ordering::Relaxed);
 
-        Self { _p: uarte }
+        Self {
+            r: T::regs(),
+            state: T::state(),
+            _p: PhantomData {},
+        }
     }
 
     /// Write all bytes in the buffer.
@@ -409,8 +428,8 @@ impl<'d, T: Instance> UarteTx<'d, T> {
         let ptr = buffer.as_ptr();
         let len = buffer.len();
 
-        let r = T::regs();
-        let s = T::state();
+        let r = self.r;
+        let s = self.state;
 
         let drop = OnDrop::new(move || {
             trace!("write drop: stopping");
@@ -479,7 +498,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
         let ptr = buffer.as_ptr();
         let len = buffer.len();
 
-        let r = T::regs();
+        let r = self.r;
 
         r.txd().ptr().write_value(ptr as u32);
         r.txd().maxcnt().write(|w| w.set_maxcnt(len as _));
@@ -501,11 +520,11 @@ impl<'d, T: Instance> UarteTx<'d, T> {
     }
 }
 
-impl<'a, T: Instance> Drop for UarteTx<'a, T> {
+impl<'a> Drop for UarteTx<'a> {
     fn drop(&mut self) {
         trace!("uarte tx drop");
 
-        let r = T::regs();
+        let r = self.r;
 
         let did_stoptx = r.events_txstarted().read() != 0;
         trace!("did_stoptx {}", did_stoptx);
@@ -513,15 +532,15 @@ impl<'a, T: Instance> Drop for UarteTx<'a, T> {
         // Wait for txstopped, if needed.
         while did_stoptx && r.events_txstopped().read() == 0 {}
 
-        let s = T::state();
+        let s = self.state;
 
         drop_tx_rx(r, s);
     }
 }
 
-impl<'d, T: Instance> UarteRx<'d, T> {
+impl<'d> UarteRx<'d> {
     /// Create a new rx-only UARTE without hardware flow control
-    pub fn new(
+    pub fn new<T: Instance>(
         uarte: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         rxd: Peri<'d, impl GpioPin>,
@@ -531,7 +550,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
     }
 
     /// Create a new rx-only UARTE with hardware flow control (RTS/CTS)
-    pub fn new_with_rtscts(
+    pub fn new_with_rtscts<T: Instance>(
         uarte: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         rxd: Peri<'d, impl GpioPin>,
@@ -543,13 +562,18 @@ impl<'d, T: Instance> UarteRx<'d, T> {
 
     /// Check for errors and clear the error register if an error occured.
     fn check_and_clear_errors(&mut self) -> Result<(), Error> {
-        let r = T::regs();
+        let r = self.r;
         let err_bits = r.errorsrc().read();
         r.errorsrc().write_value(err_bits);
         ErrorSource::from_bits_truncate(err_bits.0).check()
     }
 
-    fn new_inner(uarte: Peri<'d, T>, rxd: Peri<'d, AnyPin>, rts: Option<Peri<'d, AnyPin>>, config: Config) -> Self {
+    fn new_inner<T: Instance>(
+        _uarte: Peri<'d, T>,
+        rxd: Peri<'d, AnyPin>,
+        rts: Option<Peri<'d, AnyPin>>,
+        config: Config,
+    ) -> Self {
         let r = T::regs();
 
         configure(r, config, rts.is_some());
@@ -562,7 +586,11 @@ impl<'d, T: Instance> UarteRx<'d, T> {
         let s = T::state();
         s.tx_rx_refcount.store(1, Ordering::Relaxed);
 
-        Self { _p: uarte }
+        Self {
+            r: T::regs(),
+            state: T::state(),
+            _p: PhantomData {},
+        }
     }
 
     /// Upgrade to an instance that supports idle line detection.
@@ -571,10 +599,10 @@ impl<'d, T: Instance> UarteRx<'d, T> {
         timer: Peri<'d, U>,
         ppi_ch1: Peri<'d, impl ConfigurableChannel + 'd>,
         ppi_ch2: Peri<'d, impl ConfigurableChannel + 'd>,
-    ) -> UarteRxWithIdle<'d, T, U> {
+    ) -> UarteRxWithIdle<'d> {
         let timer = Timer::new(timer);
 
-        let r = T::regs();
+        let r = self.r;
 
         // BAUDRATE register values are `baudrate * 2^32 / 16000000`
         // source: https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values
@@ -605,11 +633,15 @@ impl<'d, T: Instance> UarteRx<'d, T> {
         );
         ppi_ch2.enable();
 
+        let state = self.state;
+
         UarteRxWithIdle {
             rx: self,
             timer,
-            ppi_ch1,
+            ppi_ch1: ppi_ch1,
             _ppi_ch2: ppi_ch2,
+            r: r,
+            state: state,
         }
     }
 
@@ -625,8 +657,8 @@ impl<'d, T: Instance> UarteRx<'d, T> {
         let ptr = buffer.as_ptr();
         let len = buffer.len();
 
-        let r = T::regs();
-        let s = T::state();
+        let r = self.r;
+        let s = self.state;
 
         let drop = OnDrop::new(move || {
             trace!("read drop: stopping");
@@ -692,7 +724,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
         let ptr = buffer.as_ptr();
         let len = buffer.len();
 
-        let r = T::regs();
+        let r = self.r;
 
         r.rxd().ptr().write_value(ptr as u32);
         r.rxd().maxcnt().write(|w| w.set_maxcnt(len as _));
@@ -718,11 +750,11 @@ impl<'d, T: Instance> UarteRx<'d, T> {
     }
 }
 
-impl<'a, T: Instance> Drop for UarteRx<'a, T> {
+impl<'a> Drop for UarteRx<'a> {
     fn drop(&mut self) {
         trace!("uarte rx drop");
 
-        let r = T::regs();
+        let r = self.r;
 
         let did_stoprx = r.events_rxstarted().read() != 0;
         trace!("did_stoprx {}", did_stoprx);
@@ -730,7 +762,7 @@ impl<'a, T: Instance> Drop for UarteRx<'a, T> {
         // Wait for rxto, if needed.
         while did_stoprx && r.events_rxto().read() == 0 {}
 
-        let s = T::state();
+        let s = self.state;
 
         drop_tx_rx(r, s);
     }
@@ -739,14 +771,16 @@ impl<'a, T: Instance> Drop for UarteRx<'a, T> {
 /// Receiver part of the UARTE driver, with `read_until_idle` support.
 ///
 /// This can be obtained via [`Uarte::split_with_idle`].
-pub struct UarteRxWithIdle<'d, T: Instance, U: TimerInstance> {
-    rx: UarteRx<'d, T>,
-    timer: Timer<'d, U>,
+pub struct UarteRxWithIdle<'d> {
+    rx: UarteRx<'d>,
+    timer: Timer<'d>,
     ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 2>,
     _ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 1>,
+    r: pac::uarte::Uarte,
+    state: &'static State,
 }
 
-impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
+impl<'d> UarteRxWithIdle<'d> {
     /// Read bytes until the buffer is filled.
     pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
         self.ppi_ch1.disable();
@@ -773,8 +807,8 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
         let ptr = buffer.as_ptr();
         let len = buffer.len();
 
-        let r = T::regs();
-        let s = T::state();
+        let r = self.r;
+        let s = self.state;
 
         self.ppi_ch1.enable();
 
@@ -846,7 +880,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
         let ptr = buffer.as_ptr();
         let len = buffer.len();
 
-        let r = T::regs();
+        let r = self.r;
 
         self.ppi_ch1.enable();
 
@@ -997,7 +1031,7 @@ macro_rules! impl_uarte {
 mod eh02 {
     use super::*;
 
-    impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for Uarte<'d, T> {
+    impl<'d> embedded_hal_02::blocking::serial::Write<u8> for Uarte<'d> {
         type Error = Error;
 
         fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
@@ -1009,7 +1043,7 @@ mod eh02 {
         }
     }
 
-    impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for UarteTx<'d, T> {
+    impl<'d> embedded_hal_02::blocking::serial::Write<u8> for UarteTx<'d> {
         type Error = Error;
 
         fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
@@ -1038,22 +1072,22 @@ mod _embedded_io {
         }
     }
 
-    impl<'d, U: Instance> embedded_io_async::ErrorType for Uarte<'d, U> {
+    impl<'d> embedded_io_async::ErrorType for Uarte<'d> {
         type Error = Error;
     }
 
-    impl<'d, U: Instance> embedded_io_async::ErrorType for UarteTx<'d, U> {
+    impl<'d> embedded_io_async::ErrorType for UarteTx<'d> {
         type Error = Error;
     }
 
-    impl<'d, U: Instance> embedded_io_async::Write for Uarte<'d, U> {
+    impl<'d> embedded_io_async::Write for Uarte<'d> {
         async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
             self.write(buf).await?;
             Ok(buf.len())
         }
     }
 
-    impl<'d: 'd, U: Instance> embedded_io_async::Write for UarteTx<'d, U> {
+    impl<'d> embedded_io_async::Write for UarteTx<'d> {
         async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
             self.write(buf).await?;
             Ok(buf.len())
diff --git a/embassy-nrf/src/usb/mod.rs b/embassy-nrf/src/usb/mod.rs
index c6970fc0f..07cf2578a 100644
--- a/embassy-nrf/src/usb/mod.rs
+++ b/embassy-nrf/src/usb/mod.rs
@@ -4,10 +4,10 @@
 
 pub mod vbus_detect;
 
-use core::future::{poll_fn, Future};
+use core::future::{Future, poll_fn};
 use core::marker::PhantomData;
 use core::mem::MaybeUninit;
-use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
+use core::sync::atomic::{AtomicU32, Ordering, compiler_fence};
 use core::task::Poll;
 
 use cortex_m::peripheral::NVIC;
@@ -86,17 +86,18 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 }
 
 /// USB driver.
-pub struct Driver<'d, T: Instance, V: VbusDetect> {
-    _p: Peri<'d, T>,
+pub struct Driver<'d, V: VbusDetect> {
+    regs: pac::usbd::Usbd,
     alloc_in: Allocator,
     alloc_out: Allocator,
     vbus_detect: V,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance, V: VbusDetect> Driver<'d, T, V> {
+impl<'d, V: VbusDetect> Driver<'d, V> {
     /// Create a new USB driver.
-    pub fn new(
-        usb: Peri<'d, T>,
+    pub fn new<T: Instance>(
+        _usb: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         vbus_detect: V,
     ) -> Self {
@@ -104,19 +105,20 @@ impl<'d, T: Instance, V: VbusDetect> Driver<'d, T, V> {
         unsafe { T::Interrupt::enable() };
 
         Self {
-            _p: usb,
+            regs: crate::pac::USBD,
             alloc_in: Allocator::new(),
             alloc_out: Allocator::new(),
             vbus_detect,
+            _phantom: PhantomData,
         }
     }
 }
 
-impl<'d, T: Instance, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, T, V> {
-    type EndpointOut = Endpoint<'d, T, Out>;
-    type EndpointIn = Endpoint<'d, T, In>;
-    type ControlPipe = ControlPipe<'d, T>;
-    type Bus = Bus<'d, T, V>;
+impl<'d, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, V> {
+    type EndpointOut = Endpoint<'d, Out>;
+    type EndpointIn = Endpoint<'d, In>;
+    type ControlPipe = ControlPipe<'d>;
+    type Bus = Bus<'d, V>;
 
     fn alloc_endpoint_in(
         &mut self,
@@ -127,12 +129,15 @@ impl<'d, T: Instance, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, T, V
     ) -> Result<Self::EndpointIn, driver::EndpointAllocError> {
         let index = self.alloc_in.allocate(ep_type, ep_addr)?;
         let ep_addr = EndpointAddress::from_parts(index, Direction::In);
-        Ok(Endpoint::new(EndpointInfo {
-            addr: ep_addr,
-            ep_type,
-            max_packet_size: packet_size,
-            interval_ms,
-        }))
+        Ok(Endpoint::new(
+            self.regs,
+            EndpointInfo {
+                addr: ep_addr,
+                ep_type,
+                max_packet_size: packet_size,
+                interval_ms,
+            },
+        ))
     }
 
     fn alloc_endpoint_out(
@@ -144,39 +149,45 @@ impl<'d, T: Instance, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, T, V
     ) -> Result<Self::EndpointOut, driver::EndpointAllocError> {
         let index = self.alloc_out.allocate(ep_type, ep_addr)?;
         let ep_addr = EndpointAddress::from_parts(index, Direction::Out);
-        Ok(Endpoint::new(EndpointInfo {
-            addr: ep_addr,
-            ep_type,
-            max_packet_size: packet_size,
-            interval_ms,
-        }))
+        Ok(Endpoint::new(
+            self.regs,
+            EndpointInfo {
+                addr: ep_addr,
+                ep_type,
+                max_packet_size: packet_size,
+                interval_ms,
+            },
+        ))
     }
 
     fn start(self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
         (
             Bus {
-                _p: unsafe { self._p.clone_unchecked() },
+                regs: self.regs,
                 power_available: false,
                 vbus_detect: self.vbus_detect,
+                _phantom: PhantomData,
             },
             ControlPipe {
-                _p: self._p,
+                regs: self.regs,
                 max_packet_size: control_max_packet_size,
+                _phantom: PhantomData,
             },
         )
     }
 }
 
 /// USB bus.
-pub struct Bus<'d, T: Instance, V: VbusDetect> {
-    _p: Peri<'d, T>,
+pub struct Bus<'d, V: VbusDetect> {
+    regs: pac::usbd::Usbd,
     power_available: bool,
     vbus_detect: V,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
+impl<'d, V: VbusDetect> driver::Bus for Bus<'d, V> {
     async fn enable(&mut self) {
-        let regs = T::regs();
+        let regs = self.regs;
 
         errata::pre_enable();
 
@@ -215,14 +226,14 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
     }
 
     async fn disable(&mut self) {
-        let regs = T::regs();
+        let regs = self.regs;
         regs.enable().write(|x| x.set_enable(false));
     }
 
     fn poll(&mut self) -> impl Future<Output = Event> {
         poll_fn(|cx| {
             BUS_WAKER.register(cx.waker());
-            let regs = T::regs();
+            let regs = self.regs;
 
             if regs.events_usbreset().read() != 0 {
                 regs.events_usbreset().write_value(0);
@@ -280,7 +291,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
     }
 
     fn endpoint_set_stalled(&mut self, ep_addr: EndpointAddress, stalled: bool) {
-        let regs = T::regs();
+        let regs = self.regs;
         if ep_addr.index() == 0 {
             if stalled {
                 regs.tasks_ep0stall().write_value(1);
@@ -298,7 +309,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
     }
 
     fn endpoint_is_stalled(&mut self, ep_addr: EndpointAddress) -> bool {
-        let regs = T::regs();
+        let regs = self.regs;
         let i = ep_addr.index();
         match ep_addr.direction() {
             Direction::Out => regs.halted().epout(i).read().getstatus() == vals::Getstatus::HALTED,
@@ -307,7 +318,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
     }
 
     fn endpoint_set_enabled(&mut self, ep_addr: EndpointAddress, enabled: bool) {
-        let regs = T::regs();
+        let regs = self.regs;
 
         let i = ep_addr.index();
         let mask = 1 << i;
@@ -319,11 +330,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
                 let mut was_enabled = false;
                 regs.epinen().modify(|w| {
                     was_enabled = (w.0 & mask) != 0;
-                    if enabled {
-                        w.0 |= mask
-                    } else {
-                        w.0 &= !mask
-                    }
+                    if enabled { w.0 |= mask } else { w.0 &= !mask }
                 });
 
                 let ready_mask = In::mask(i);
@@ -359,7 +366,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
 
     #[inline]
     async fn remote_wakeup(&mut self) -> Result<(), Unsupported> {
-        let regs = T::regs();
+        let regs = self.regs;
 
         if regs.lowpower().read().lowpower() == vals::Lowpower::LOW_POWER {
             errata::pre_wakeup();
@@ -368,7 +375,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
 
             poll_fn(|cx| {
                 BUS_WAKER.register(cx.waker());
-                let regs = T::regs();
+                let regs = self.regs;
                 let r = regs.eventcause().read();
 
                 if regs.events_usbreset().read() != 0 {
@@ -441,21 +448,23 @@ impl EndpointDir for Out {
 }
 
 /// USB endpoint.
-pub struct Endpoint<'d, T: Instance, Dir> {
-    _phantom: PhantomData<(&'d mut T, Dir)>,
+pub struct Endpoint<'d, Dir> {
+    regs: pac::usbd::Usbd,
     info: EndpointInfo,
+    _phantom: PhantomData<(&'d (), Dir)>,
 }
 
-impl<'d, T: Instance, Dir> Endpoint<'d, T, Dir> {
-    fn new(info: EndpointInfo) -> Self {
+impl<'d, Dir> Endpoint<'d, Dir> {
+    fn new(regs: pac::usbd::Usbd, info: EndpointInfo) -> Self {
         Self {
+            regs,
             info,
             _phantom: PhantomData,
         }
     }
 }
 
-impl<'d, T: Instance, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, T, Dir> {
+impl<'d, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, Dir> {
     fn info(&self) -> &EndpointInfo {
         &self.info
     }
@@ -466,14 +475,14 @@ impl<'d, T: Instance, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, T, Dir
 }
 
 #[allow(private_bounds)]
-impl<'d, T: Instance, Dir: EndpointDir> Endpoint<'d, T, Dir> {
-    fn wait_enabled_state(&mut self, state: bool) -> impl Future<Output = ()> {
+impl<'d, Dir: EndpointDir> Endpoint<'d, Dir> {
+    fn wait_enabled_state(&mut self, state: bool) -> impl Future<Output = ()> + use<'_, 'd, Dir> {
         let i = self.info.addr.index();
         assert!(i != 0);
 
         poll_fn(move |cx| {
             Dir::waker(i).register(cx.waker());
-            if Dir::is_enabled(T::regs(), i) == state {
+            if Dir::is_enabled(self.regs, i) == state {
                 Poll::Ready(())
             } else {
                 Poll::Pending
@@ -482,12 +491,12 @@ impl<'d, T: Instance, Dir: EndpointDir> Endpoint<'d, T, Dir> {
     }
 
     /// Wait for the endpoint to be disabled
-    pub fn wait_disabled(&mut self) -> impl Future<Output = ()> {
+    pub fn wait_disabled(&mut self) -> impl Future<Output = ()> + use<'_, 'd, Dir> {
         self.wait_enabled_state(false)
     }
 }
 
-impl<'d, T: Instance, Dir> Endpoint<'d, T, Dir> {
+impl<'d, Dir> Endpoint<'d, Dir> {
     async fn wait_data_ready(&mut self) -> Result<(), ()>
     where
         Dir: EndpointDir,
@@ -497,7 +506,7 @@ impl<'d, T: Instance, Dir> Endpoint<'d, T, Dir> {
         poll_fn(|cx| {
             Dir::waker(i).register(cx.waker());
             let r = READY_ENDPOINTS.load(Ordering::Acquire);
-            if !Dir::is_enabled(T::regs(), i) {
+            if !Dir::is_enabled(self.regs, i) {
                 Poll::Ready(Err(()))
             } else if r & Dir::mask(i) != 0 {
                 Poll::Ready(Ok(()))
@@ -514,9 +523,7 @@ impl<'d, T: Instance, Dir> Endpoint<'d, T, Dir> {
     }
 }
 
-unsafe fn read_dma<T: Instance>(i: usize, buf: &mut [u8]) -> Result<usize, EndpointError> {
-    let regs = T::regs();
-
+unsafe fn read_dma(regs: pac::usbd::Usbd, i: usize, buf: &mut [u8]) -> Result<usize, EndpointError> {
     // Check that the packet fits into the buffer
     let size = regs.size().epout(i).read().0 as usize;
     if size > buf.len() {
@@ -539,8 +546,7 @@ unsafe fn read_dma<T: Instance>(i: usize, buf: &mut [u8]) -> Result<usize, Endpo
     Ok(size)
 }
 
-unsafe fn write_dma<T: Instance>(i: usize, buf: &[u8]) {
-    let regs = T::regs();
+unsafe fn write_dma(regs: pac::usbd::Usbd, i: usize, buf: &[u8]) {
     assert!(buf.len() <= 64);
 
     let mut ram_buf: MaybeUninit<[u8; 64]> = MaybeUninit::uninit();
@@ -566,43 +572,44 @@ unsafe fn write_dma<T: Instance>(i: usize, buf: &[u8]) {
     dma_end();
 }
 
-impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
+impl<'d> driver::EndpointOut for Endpoint<'d, Out> {
     async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
         let i = self.info.addr.index();
         assert!(i != 0);
 
         self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?;
 
-        unsafe { read_dma::<T>(i, buf) }
+        unsafe { read_dma(self.regs, i, buf) }
     }
 }
 
-impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
+impl<'d> driver::EndpointIn for Endpoint<'d, In> {
     async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError> {
         let i = self.info.addr.index();
         assert!(i != 0);
 
         self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?;
 
-        unsafe { write_dma::<T>(i, buf) }
+        unsafe { write_dma(self.regs, i, buf) }
 
         Ok(())
     }
 }
 
 /// USB control pipe.
-pub struct ControlPipe<'d, T: Instance> {
-    _p: Peri<'d, T>,
+pub struct ControlPipe<'d> {
+    regs: pac::usbd::Usbd,
     max_packet_size: u16,
+    _phantom: PhantomData<&'d ()>,
 }
 
-impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
+impl<'d> driver::ControlPipe for ControlPipe<'d> {
     fn max_packet_size(&self) -> usize {
         usize::from(self.max_packet_size)
     }
 
     async fn setup(&mut self) -> [u8; 8] {
-        let regs = T::regs();
+        let regs = self.regs;
 
         // Reset shorts
         regs.shorts().write(|_| ());
@@ -611,7 +618,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
         regs.intenset().write(|w| w.set_ep0setup(true));
         poll_fn(|cx| {
             EP0_WAKER.register(cx.waker());
-            let regs = T::regs();
+            let regs = self.regs;
             if regs.events_ep0setup().read() != 0 {
                 Poll::Ready(())
             } else {
@@ -636,7 +643,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
     }
 
     async fn data_out(&mut self, buf: &mut [u8], _first: bool, _last: bool) -> Result<usize, EndpointError> {
-        let regs = T::regs();
+        let regs = self.regs;
 
         regs.events_ep0datadone().write_value(0);
 
@@ -651,7 +658,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
         });
         poll_fn(|cx| {
             EP0_WAKER.register(cx.waker());
-            let regs = T::regs();
+            let regs = self.regs;
             if regs.events_ep0datadone().read() != 0 {
                 Poll::Ready(Ok(()))
             } else if regs.events_usbreset().read() != 0 {
@@ -666,17 +673,17 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
         })
         .await?;
 
-        unsafe { read_dma::<T>(0, buf) }
+        unsafe { read_dma(self.regs, 0, buf) }
     }
 
     async fn data_in(&mut self, buf: &[u8], _first: bool, last: bool) -> Result<(), EndpointError> {
-        let regs = T::regs();
+        let regs = self.regs;
         regs.events_ep0datadone().write_value(0);
 
         regs.shorts().write(|w| w.set_ep0datadone_ep0status(last));
 
         // This starts a TX on EP0. events_ep0datadone notifies when done.
-        unsafe { write_dma::<T>(0, buf) }
+        unsafe { write_dma(self.regs, 0, buf) }
 
         regs.intenset().write(|w| {
             w.set_usbreset(true);
@@ -687,7 +694,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
         poll_fn(|cx| {
             cx.waker().wake_by_ref();
             EP0_WAKER.register(cx.waker());
-            let regs = T::regs();
+            let regs = self.regs;
             if regs.events_ep0datadone().read() != 0 {
                 Poll::Ready(Ok(()))
             } else if regs.events_usbreset().read() != 0 {
@@ -704,12 +711,12 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
     }
 
     async fn accept(&mut self) {
-        let regs = T::regs();
+        let regs = self.regs;
         regs.tasks_ep0status().write_value(1);
     }
 
     async fn reject(&mut self) {
-        let regs = T::regs();
+        let regs = self.regs;
         regs.tasks_ep0stall().write_value(1);
     }
 
diff --git a/embassy-nrf/src/usb/vbus_detect.rs b/embassy-nrf/src/usb/vbus_detect.rs
index 33cf91ee2..f24a7bff5 100644
--- a/embassy-nrf/src/usb/vbus_detect.rs
+++ b/embassy-nrf/src/usb/vbus_detect.rs
@@ -1,6 +1,6 @@
 //! Trait and implementations for performing VBUS detection.
 
-use core::future::{poll_fn, Future};
+use core::future::{Future, poll_fn};
 use core::sync::atomic::{AtomicBool, Ordering};
 use core::task::Poll;
 
diff --git a/embassy-nrf/src/util.rs b/embassy-nrf/src/util.rs
index 78f71719f..87118d347 100644
--- a/embassy-nrf/src/util.rs
+++ b/embassy-nrf/src/util.rs
@@ -15,9 +15,5 @@ pub(crate) fn slice_in_ram<T>(slice: *const [T]) -> bool {
 
 /// Return an error if slice is not in RAM. Skips check if slice is zero-length.
 pub(crate) fn slice_in_ram_or<T, E>(slice: *const [T], err: E) -> Result<(), E> {
-    if slice_in_ram(slice) {
-        Ok(())
-    } else {
-        Err(err)
-    }
+    if slice_in_ram(slice) { Ok(()) } else { Err(err) }
 }
diff --git a/embassy-nrf/src/wdt.rs b/embassy-nrf/src/wdt.rs
index 7ab9adc29..6afd73431 100644
--- a/embassy-nrf/src/wdt.rs
+++ b/embassy-nrf/src/wdt.rs
@@ -11,7 +11,7 @@ use embassy_hal_internal::PeripheralType;
 
 use crate::pac::wdt::vals;
 pub use crate::pac::wdt::vals::{Halt as HaltConfig, Sleep as SleepConfig};
-use crate::{interrupt, pac, peripherals, Peri};
+use crate::{Peri, interrupt, pac, peripherals};
 
 const MIN_TICKS: u32 = 15;
 
@@ -66,11 +66,11 @@ impl Default for Config {
 }
 
 /// Watchdog driver.
-pub struct Watchdog<T: Instance> {
-    _wdt: Peri<'static, T>,
+pub struct Watchdog {
+    r: pac::wdt::Wdt,
 }
 
-impl<T: Instance> Watchdog<T> {
+impl Watchdog {
     /// Try to create a new watchdog driver.
     ///
     /// This function will return an error if the watchdog is already active
@@ -79,7 +79,7 @@ impl<T: Instance> Watchdog<T> {
     ///
     /// `N` must be between 1 and 8, inclusive.
     #[inline]
-    pub fn try_new<const N: usize>(
+    pub fn try_new<T: Instance, const N: usize>(
         wdt: Peri<'static, T>,
         config: Config,
     ) -> Result<(Self, [WatchdogHandle; N]), Peri<'static, T>> {
@@ -116,7 +116,7 @@ impl<T: Instance> Watchdog<T> {
             r.tasks_start().write_value(1);
         }
 
-        let this = Self { _wdt: wdt };
+        let this = Self { r: T::REGS };
 
         let mut handles = [const { WatchdogHandle { index: 0 } }; N];
         for i in 0..N {
@@ -135,7 +135,7 @@ impl<T: Instance> Watchdog<T> {
     /// interrupt has been enabled.
     #[inline(always)]
     pub fn enable_interrupt(&mut self) {
-        T::REGS.intenset().write(|w| w.set_timeout(true));
+        self.r.intenset().write(|w| w.set_timeout(true));
     }
 
     /// Disable the watchdog interrupt.
@@ -143,7 +143,7 @@ impl<T: Instance> Watchdog<T> {
     /// NOTE: This has no effect on the reset caused by the Watchdog.
     #[inline(always)]
     pub fn disable_interrupt(&mut self) {
-        T::REGS.intenclr().write(|w| w.set_timeout(true));
+        self.r.intenclr().write(|w| w.set_timeout(true));
     }
 
     /// Is the watchdog still awaiting pets from any handle?
@@ -152,9 +152,8 @@ impl<T: Instance> Watchdog<T> {
     /// handles to prevent a reset this time period.
     #[inline(always)]
     pub fn awaiting_pets(&self) -> bool {
-        let r = T::REGS;
-        let enabled = r.rren().read().0;
-        let status = r.reqstatus().read().0;
+        let enabled = self.r.rren().read().0;
+        let status = self.r.reqstatus().read().0;
         (status & enabled) == 0
     }
 }