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authorDario Nieuwenhuis <[email protected]>2022-03-30 02:01:09 +0200
committerDario Nieuwenhuis <[email protected]>2022-04-06 05:38:11 +0200
commita435d78cf78deb1a93682d9ff2632706eaa1b951 (patch)
tree580f4ac3aba6ede0a3021982c9725a6d3055b251 /embassy-nrf/src
parent60d3d111972f462c1f38d1d4fd27e89713974fc6 (diff)
usb: cleanup and simplify error handling.
Diffstat (limited to 'embassy-nrf/src')
-rw-r--r--embassy-nrf/src/usb.rs18
1 files changed, 7 insertions, 11 deletions
diff --git a/embassy-nrf/src/usb.rs b/embassy-nrf/src/usb.rs
index d9524675d..1057d880c 100644
--- a/embassy-nrf/src/usb.rs
+++ b/embassy-nrf/src/usb.rs
@@ -403,11 +403,9 @@ unsafe fn read_dma<T: Instance>(i: usize, buf: &mut [u8]) -> Result<usize, ReadE
403 Ok(size) 403 Ok(size)
404} 404}
405 405
406unsafe fn write_dma<T: Instance>(i: usize, buf: &[u8]) -> Result<(), WriteError> { 406unsafe fn write_dma<T: Instance>(i: usize, buf: &[u8]) {
407 let regs = T::regs(); 407 let regs = T::regs();
408 if buf.len() > 64 { 408 assert!(buf.len() <= 64);
409 return Err(WriteError::BufferOverflow);
410 }
411 409
412 let mut ram_buf: MaybeUninit<[u8; 64]> = MaybeUninit::uninit(); 410 let mut ram_buf: MaybeUninit<[u8; 64]> = MaybeUninit::uninit();
413 let ptr = if !slice_in_ram(buf) { 411 let ptr = if !slice_in_ram(buf) {
@@ -441,8 +439,6 @@ unsafe fn write_dma<T: Instance>(i: usize, buf: &[u8]) -> Result<(), WriteError>
441 regs.tasks_startepin[i].write(|w| w.bits(1)); 439 regs.tasks_startepin[i].write(|w| w.bits(1));
442 while regs.events_endepin[i].read().bits() == 0 {} 440 while regs.events_endepin[i].read().bits() == 0 {}
443 dma_end(); 441 dma_end();
444
445 Ok(())
446} 442}
447 443
448impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> { 444impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
@@ -497,6 +493,8 @@ impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
497 READY_ENDPOINTS.fetch_and(!(1 << i), Ordering::AcqRel); 493 READY_ENDPOINTS.fetch_and(!(1 << i), Ordering::AcqRel);
498 494
499 unsafe { write_dma::<T>(i, buf) } 495 unsafe { write_dma::<T>(i, buf) }
496
497 Ok(())
500 } 498 }
501 } 499 }
502} 500}
@@ -535,9 +533,7 @@ impl<'d, T: Instance> ControlPipe<'d, T> {
535 async fn write(&mut self, buf: &[u8], last_chunk: bool) { 533 async fn write(&mut self, buf: &[u8], last_chunk: bool) {
536 let regs = T::regs(); 534 let regs = T::regs();
537 regs.events_ep0datadone.reset(); 535 regs.events_ep0datadone.reset();
538 unsafe { 536 unsafe { write_dma::<T>(0, buf) }
539 write_dma::<T>(0, buf).unwrap();
540 }
541 537
542 regs.shorts 538 regs.shorts
543 .modify(|_, w| w.ep0datadone_ep0status().bit(last_chunk)); 539 .modify(|_, w| w.ep0datadone_ep0status().bit(last_chunk));
@@ -616,7 +612,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
616 612
617 fn data_out<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::DataOutFuture<'a> { 613 fn data_out<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::DataOutFuture<'a> {
618 async move { 614 async move {
619 let req = self.request.unwrap(); 615 let req = unwrap!(self.request);
620 assert!(req.direction == UsbDirection::Out); 616 assert!(req.direction == UsbDirection::Out);
621 assert!(req.length > 0); 617 assert!(req.length > 0);
622 618
@@ -649,7 +645,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
649 debug!("control in accept {:x}", buf); 645 debug!("control in accept {:x}", buf);
650 #[cfg(not(feature = "defmt"))] 646 #[cfg(not(feature = "defmt"))]
651 debug!("control in accept {:x?}", buf); 647 debug!("control in accept {:x?}", buf);
652 let req = self.request.unwrap(); 648 let req = unwrap!(self.request);
653 assert!(req.direction == UsbDirection::In); 649 assert!(req.direction == UsbDirection::In);
654 650
655 let req_len = usize::from(req.length); 651 let req_len = usize::from(req.length);