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authorDario Nieuwenhuis <[email protected]>2024-11-15 02:22:20 +0100
committerDario Nieuwenhuis <[email protected]>2024-11-15 02:22:20 +0100
commit3f23fd5c98244921b97858912bbcdfd681b4f92e (patch)
treee572b5ebc9dae3c2fedf97b576f188498832220a /embassy-nrf
parentea1b97ed4032d5f925839165c546833323ef1b01 (diff)
Update nrf-pac.
Diffstat (limited to 'embassy-nrf')
-rw-r--r--embassy-nrf/Cargo.toml2
-rw-r--r--embassy-nrf/src/chips/nrf51.rs8
-rw-r--r--embassy-nrf/src/chips/nrf52805.rs28
-rw-r--r--embassy-nrf/src/chips/nrf52810.rs28
-rw-r--r--embassy-nrf/src/chips/nrf52811.rs36
-rw-r--r--embassy-nrf/src/chips/nrf52820.rs52
-rw-r--r--embassy-nrf/src/chips/nrf52832.rs60
-rw-r--r--embassy-nrf/src/chips/nrf52833.rs60
-rw-r--r--embassy-nrf/src/chips/nrf52840.rs60
-rw-r--r--embassy-nrf/src/chips/nrf5340_app.rs363
-rw-r--r--embassy-nrf/src/chips/nrf5340_net.rs48
-rw-r--r--embassy-nrf/src/chips/nrf9120.rs329
-rw-r--r--embassy-nrf/src/chips/nrf9160.rs329
-rw-r--r--embassy-nrf/src/lib.rs2
-rw-r--r--embassy-nrf/src/time_driver.rs2
-rw-r--r--embassy-nrf/src/usb/vbus_detect.rs4
16 files changed, 592 insertions, 819 deletions
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 24a3db91d..7b20d2643 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -136,7 +136,7 @@ embedded-hal-async = { version = "1.0" }
136embedded-io = { version = "0.6.0" } 136embedded-io = { version = "0.6.0" }
137embedded-io-async = { version = "0.6.1" } 137embedded-io-async = { version = "0.6.1" }
138 138
139nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "875a29629cc1c87aae00cfea647a956b3807d8be" } 139nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "12e2461859acb0bfea9b2ef5cd73f1283c139ac0" }
140 140
141defmt = { version = "0.3", optional = true } 141defmt = { version = "0.3", optional = true }
142bitflags = "2.4.2" 142bitflags = "2.4.2"
diff --git a/embassy-nrf/src/chips/nrf51.rs b/embassy-nrf/src/chips/nrf51.rs
index 95fa926c3..a0365a6ee 100644
--- a/embassy-nrf/src/chips/nrf51.rs
+++ b/embassy-nrf/src/chips/nrf51.rs
@@ -146,11 +146,11 @@ impl_pin!(P0_31, 0, 31);
146impl_radio!(RADIO, RADIO, RADIO); 146impl_radio!(RADIO, RADIO, RADIO);
147 147
148embassy_hal_internal::interrupt_mod!( 148embassy_hal_internal::interrupt_mod!(
149 POWER_CLOCK, 149 CLOCK_POWER,
150 RADIO, 150 RADIO,
151 UART0, 151 UART0,
152 SPI0_TWI0, 152 TWISPI0,
153 SPI1_TWI1, 153 TWISPI1,
154 GPIOTE, 154 GPIOTE,
155 ADC, 155 ADC,
156 TIMER0, 156 TIMER0,
@@ -160,7 +160,7 @@ embassy_hal_internal::interrupt_mod!(
160 TEMP, 160 TEMP,
161 RNG, 161 RNG,
162 ECB, 162 ECB,
163 CCM_AAR, 163 AAR_CCM,
164 WDT, 164 WDT,
165 RTC1, 165 RTC1,
166 QDEC, 166 QDEC,
diff --git a/embassy-nrf/src/chips/nrf52805.rs b/embassy-nrf/src/chips/nrf52805.rs
index fc8db856c..a9cbccec4 100644
--- a/embassy-nrf/src/chips/nrf52805.rs
+++ b/embassy-nrf/src/chips/nrf52805.rs
@@ -138,15 +138,15 @@ embassy_hal_internal::peripherals! {
138 EGU1, 138 EGU1,
139} 139}
140 140
141impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); 141impl_uarte!(UARTE0, UARTE0, UARTE0);
142 142
143impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0); 143impl_spim!(SPI0, SPIM0, SPI0);
144 144
145impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0); 145impl_spis!(SPI0, SPIS0, SPI0);
146 146
147impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0); 147impl_twim!(TWI0, TWIM0, TWI0);
148 148
149impl_twis!(TWI0, TWIS0, TWIM0_TWIS0_TWI0); 149impl_twis!(TWI0, TWIS0, TWI0);
150 150
151impl_qdec!(QDEC, QDEC, QDEC); 151impl_qdec!(QDEC, QDEC, QDEC);
152 152
@@ -218,15 +218,15 @@ impl_saadc_input!(P0_05, ANALOG_INPUT3);
218 218
219impl_radio!(RADIO, RADIO, RADIO); 219impl_radio!(RADIO, RADIO, RADIO);
220 220
221impl_egu!(EGU0, EGU0, SWI0_EGU0); 221impl_egu!(EGU0, EGU0, EGU0_SWI0);
222impl_egu!(EGU1, EGU1, SWI1_EGU1); 222impl_egu!(EGU1, EGU1, EGU1_SWI1);
223 223
224embassy_hal_internal::interrupt_mod!( 224embassy_hal_internal::interrupt_mod!(
225 POWER_CLOCK, 225 CLOCK_POWER,
226 RADIO, 226 RADIO,
227 UARTE0_UART0, 227 UARTE0,
228 TWIM0_TWIS0_TWI0, 228 TWI0,
229 SPIM0_SPIS0_SPI0, 229 SPI0,
230 GPIOTE, 230 GPIOTE,
231 SAADC, 231 SAADC,
232 TIMER0, 232 TIMER0,
@@ -236,12 +236,12 @@ embassy_hal_internal::interrupt_mod!(
236 TEMP, 236 TEMP,
237 RNG, 237 RNG,
238 ECB, 238 ECB,
239 CCM_AAR, 239 AAR_CCM,
240 WDT, 240 WDT,
241 RTC1, 241 RTC1,
242 QDEC, 242 QDEC,
243 SWI0_EGU0, 243 EGU0_SWI0,
244 SWI1_EGU1, 244 EGU1_SWI1,
245 SWI2, 245 SWI2,
246 SWI3, 246 SWI3,
247 SWI4, 247 SWI4,
diff --git a/embassy-nrf/src/chips/nrf52810.rs b/embassy-nrf/src/chips/nrf52810.rs
index 11a8b4dde..ca31c35e1 100644
--- a/embassy-nrf/src/chips/nrf52810.rs
+++ b/embassy-nrf/src/chips/nrf52810.rs
@@ -144,15 +144,15 @@ embassy_hal_internal::peripherals! {
144 EGU1, 144 EGU1,
145} 145}
146 146
147impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); 147impl_uarte!(UARTE0, UARTE0, UARTE0);
148 148
149impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0); 149impl_spim!(SPI0, SPIM0, SPI0);
150 150
151impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0); 151impl_spis!(SPI0, SPIS0, SPI0);
152 152
153impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0); 153impl_twim!(TWI0, TWIM0, TWI0);
154 154
155impl_twis!(TWI0, TWIS0, TWIM0_TWIS0_TWI0); 155impl_twis!(TWI0, TWIS0, TWI0);
156 156
157impl_pwm!(PWM0, PWM0, PWM0); 157impl_pwm!(PWM0, PWM0, PWM0);
158 158
@@ -244,15 +244,15 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
244 244
245impl_radio!(RADIO, RADIO, RADIO); 245impl_radio!(RADIO, RADIO, RADIO);
246 246
247impl_egu!(EGU0, EGU0, SWI0_EGU0); 247impl_egu!(EGU0, EGU0, EGU0_SWI0);
248impl_egu!(EGU1, EGU1, SWI1_EGU1); 248impl_egu!(EGU1, EGU1, EGU1_SWI1);
249 249
250embassy_hal_internal::interrupt_mod!( 250embassy_hal_internal::interrupt_mod!(
251 POWER_CLOCK, 251 CLOCK_POWER,
252 RADIO, 252 RADIO,
253 UARTE0_UART0, 253 UARTE0,
254 TWIM0_TWIS0_TWI0, 254 TWI0,
255 SPIM0_SPIS0_SPI0, 255 SPI0,
256 GPIOTE, 256 GPIOTE,
257 SAADC, 257 SAADC,
258 TIMER0, 258 TIMER0,
@@ -262,13 +262,13 @@ embassy_hal_internal::interrupt_mod!(
262 TEMP, 262 TEMP,
263 RNG, 263 RNG,
264 ECB, 264 ECB,
265 CCM_AAR, 265 AAR_CCM,
266 WDT, 266 WDT,
267 RTC1, 267 RTC1,
268 QDEC, 268 QDEC,
269 COMP, 269 COMP,
270 SWI0_EGU0, 270 EGU0_SWI0,
271 SWI1_EGU1, 271 EGU1_SWI1,
272 SWI2, 272 SWI2,
273 SWI3, 273 SWI3,
274 SWI4, 274 SWI4,
diff --git a/embassy-nrf/src/chips/nrf52811.rs b/embassy-nrf/src/chips/nrf52811.rs
index 077a36e31..caf3fdcf8 100644
--- a/embassy-nrf/src/chips/nrf52811.rs
+++ b/embassy-nrf/src/chips/nrf52811.rs
@@ -27,8 +27,8 @@ embassy_hal_internal::peripherals! {
27 UARTE0, 27 UARTE0,
28 28
29 // SPI/TWI 29 // SPI/TWI
30 TWISPI0, 30 TWI0_SPI1,
31 SPI1, 31 SPI0,
32 32
33 // SAADC 33 // SAADC
34 SAADC, 34 SAADC,
@@ -144,17 +144,17 @@ embassy_hal_internal::peripherals! {
144 EGU1, 144 EGU1,
145} 145}
146 146
147impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); 147impl_uarte!(UARTE0, UARTE0, UARTE0);
148 148
149impl_spim!(TWISPI0, SPIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); 149impl_spim!(SPI0, SPIM0, SPI0);
150impl_spim!(SPI1, SPIM1, SPIM1_SPIS1_SPI1); 150impl_spim!(TWI0_SPI1, SPIM1, TWI0_SPI1);
151 151
152impl_spis!(TWISPI0, SPIS0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); 152impl_spis!(SPI0, SPIS0, SPI0);
153impl_spis!(SPI1, SPIS1, SPIM1_SPIS1_SPI1); 153impl_spis!(TWI0_SPI1, SPIS1, TWI0_SPI1);
154 154
155impl_twim!(TWISPI0, TWIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); 155impl_twim!(TWI0_SPI1, TWIM0, TWI0_SPI1);
156 156
157impl_twis!(TWISPI0, TWIS0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); 157impl_twis!(TWI0_SPI1, TWIS0, TWI0_SPI1);
158 158
159impl_pwm!(PWM0, PWM0, PWM0); 159impl_pwm!(PWM0, PWM0, PWM0);
160 160
@@ -246,15 +246,15 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
246 246
247impl_radio!(RADIO, RADIO, RADIO); 247impl_radio!(RADIO, RADIO, RADIO);
248 248
249impl_egu!(EGU0, EGU0, SWI0_EGU0); 249impl_egu!(EGU0, EGU0, EGU0_SWI0);
250impl_egu!(EGU1, EGU1, SWI1_EGU1); 250impl_egu!(EGU1, EGU1, EGU1_SWI1);
251 251
252embassy_hal_internal::interrupt_mod!( 252embassy_hal_internal::interrupt_mod!(
253 POWER_CLOCK, 253 CLOCK_POWER,
254 RADIO, 254 RADIO,
255 UARTE0_UART0, 255 UARTE0,
256 TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0, 256 TWI0_SPI1,
257 SPIM1_SPIS1_SPI1, 257 SPI0,
258 GPIOTE, 258 GPIOTE,
259 SAADC, 259 SAADC,
260 TIMER0, 260 TIMER0,
@@ -264,13 +264,13 @@ embassy_hal_internal::interrupt_mod!(
264 TEMP, 264 TEMP,
265 RNG, 265 RNG,
266 ECB, 266 ECB,
267 CCM_AAR, 267 AAR_CCM,
268 WDT, 268 WDT,
269 RTC1, 269 RTC1,
270 QDEC, 270 QDEC,
271 COMP, 271 COMP,
272 SWI0_EGU0, 272 EGU0_SWI0,
273 SWI1_EGU1, 273 EGU1_SWI1,
274 SWI2, 274 SWI2,
275 SWI3, 275 SWI3,
276 SWI4, 276 SWI4,
diff --git a/embassy-nrf/src/chips/nrf52820.rs b/embassy-nrf/src/chips/nrf52820.rs
index 6ee16706d..39573e4a5 100644
--- a/embassy-nrf/src/chips/nrf52820.rs
+++ b/embassy-nrf/src/chips/nrf52820.rs
@@ -145,19 +145,19 @@ embassy_hal_internal::peripherals! {
145 145
146impl_usb!(USBD, USBD, USBD); 146impl_usb!(USBD, USBD, USBD);
147 147
148impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); 148impl_uarte!(UARTE0, UARTE0, UARTE0);
149 149
150impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 150impl_spim!(TWISPI0, SPIM0, TWISPI0);
151impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 151impl_spim!(TWISPI1, SPIM1, TWISPI1);
152 152
153impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 153impl_spis!(TWISPI0, SPIS0, TWISPI0);
154impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 154impl_spis!(TWISPI1, SPIS1, TWISPI1);
155 155
156impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 156impl_twim!(TWISPI0, TWIM0, TWISPI0);
157impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 157impl_twim!(TWISPI1, TWIM1, TWISPI1);
158 158
159impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 159impl_twis!(TWISPI0, TWIS0, TWISPI0);
160impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 160impl_twis!(TWISPI1, TWIS1, TWISPI1);
161 161
162impl_timer!(TIMER0, TIMER0, TIMER0); 162impl_timer!(TIMER0, TIMER0, TIMER0);
163impl_timer!(TIMER1, TIMER1, TIMER1); 163impl_timer!(TIMER1, TIMER1, TIMER1);
@@ -237,19 +237,19 @@ impl_ppi_channel!(PPI_CH31, 31 => static);
237 237
238impl_radio!(RADIO, RADIO, RADIO); 238impl_radio!(RADIO, RADIO, RADIO);
239 239
240impl_egu!(EGU0, EGU0, SWI0_EGU0); 240impl_egu!(EGU0, EGU0, EGU0_SWI0);
241impl_egu!(EGU1, EGU1, SWI1_EGU1); 241impl_egu!(EGU1, EGU1, EGU1_SWI1);
242impl_egu!(EGU2, EGU2, SWI2_EGU2); 242impl_egu!(EGU2, EGU2, EGU2_SWI2);
243impl_egu!(EGU3, EGU3, SWI3_EGU3); 243impl_egu!(EGU3, EGU3, EGU3_SWI3);
244impl_egu!(EGU4, EGU4, SWI4_EGU4); 244impl_egu!(EGU4, EGU4, EGU4_SWI4);
245impl_egu!(EGU5, EGU5, SWI5_EGU5); 245impl_egu!(EGU5, EGU5, EGU5_SWI5);
246 246
247embassy_hal_internal::interrupt_mod!( 247embassy_hal_internal::interrupt_mod!(
248 POWER_CLOCK, 248 CLOCK_POWER,
249 RADIO, 249 RADIO,
250 UARTE0_UART0, 250 UARTE0,
251 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, 251 TWISPI0,
252 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, 252 TWISPI1,
253 GPIOTE, 253 GPIOTE,
254 TIMER0, 254 TIMER0,
255 TIMER1, 255 TIMER1,
@@ -258,17 +258,17 @@ embassy_hal_internal::interrupt_mod!(
258 TEMP, 258 TEMP,
259 RNG, 259 RNG,
260 ECB, 260 ECB,
261 CCM_AAR, 261 AAR_CCM,
262 WDT, 262 WDT,
263 RTC1, 263 RTC1,
264 QDEC, 264 QDEC,
265 COMP, 265 COMP,
266 SWI0_EGU0, 266 EGU0_SWI0,
267 SWI1_EGU1, 267 EGU1_SWI1,
268 SWI2_EGU2, 268 EGU2_SWI2,
269 SWI3_EGU3, 269 EGU3_SWI3,
270 SWI4_EGU4, 270 EGU4_SWI4,
271 SWI5_EGU5, 271 EGU5_SWI5,
272 TIMER3, 272 TIMER3,
273 USBD, 273 USBD,
274); 274);
diff --git a/embassy-nrf/src/chips/nrf52832.rs b/embassy-nrf/src/chips/nrf52832.rs
index 4a7a29229..7ff58d63e 100644
--- a/embassy-nrf/src/chips/nrf52832.rs
+++ b/embassy-nrf/src/chips/nrf52832.rs
@@ -163,21 +163,21 @@ embassy_hal_internal::peripherals! {
163 EGU5, 163 EGU5,
164} 164}
165 165
166impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); 166impl_uarte!(UARTE0, UARTE0, UARTE0);
167 167
168impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 168impl_spim!(TWISPI0, SPIM0, TWISPI0);
169impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 169impl_spim!(TWISPI1, SPIM1, TWISPI1);
170impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2); 170impl_spim!(SPI2, SPIM2, SPI2);
171 171
172impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 172impl_spis!(TWISPI0, SPIS0, TWISPI0);
173impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 173impl_spis!(TWISPI1, SPIS1, TWISPI1);
174impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2); 174impl_spis!(SPI2, SPIS2, SPI2);
175 175
176impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 176impl_twim!(TWISPI0, TWIM0, TWISPI0);
177impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 177impl_twim!(TWISPI1, TWIM1, TWISPI1);
178 178
179impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 179impl_twis!(TWISPI0, TWIS0, TWISPI0);
180impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 180impl_twis!(TWISPI1, TWIS1, TWISPI1);
181 181
182impl_pwm!(PWM0, PWM0, PWM0); 182impl_pwm!(PWM0, PWM0, PWM0);
183impl_pwm!(PWM1, PWM1, PWM1); 183impl_pwm!(PWM1, PWM1, PWM1);
@@ -277,19 +277,19 @@ impl_i2s!(I2S, I2S, I2S);
277 277
278impl_radio!(RADIO, RADIO, RADIO); 278impl_radio!(RADIO, RADIO, RADIO);
279 279
280impl_egu!(EGU0, EGU0, SWI0_EGU0); 280impl_egu!(EGU0, EGU0, EGU0_SWI0);
281impl_egu!(EGU1, EGU1, SWI1_EGU1); 281impl_egu!(EGU1, EGU1, EGU1_SWI1);
282impl_egu!(EGU2, EGU2, SWI2_EGU2); 282impl_egu!(EGU2, EGU2, EGU2_SWI2);
283impl_egu!(EGU3, EGU3, SWI3_EGU3); 283impl_egu!(EGU3, EGU3, EGU3_SWI3);
284impl_egu!(EGU4, EGU4, SWI4_EGU4); 284impl_egu!(EGU4, EGU4, EGU4_SWI4);
285impl_egu!(EGU5, EGU5, SWI5_EGU5); 285impl_egu!(EGU5, EGU5, EGU5_SWI5);
286 286
287embassy_hal_internal::interrupt_mod!( 287embassy_hal_internal::interrupt_mod!(
288 POWER_CLOCK, 288 CLOCK_POWER,
289 RADIO, 289 RADIO,
290 UARTE0_UART0, 290 UARTE0,
291 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, 291 TWISPI0,
292 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, 292 TWISPI1,
293 NFCT, 293 NFCT,
294 GPIOTE, 294 GPIOTE,
295 SAADC, 295 SAADC,
@@ -300,17 +300,17 @@ embassy_hal_internal::interrupt_mod!(
300 TEMP, 300 TEMP,
301 RNG, 301 RNG,
302 ECB, 302 ECB,
303 CCM_AAR, 303 AAR_CCM,
304 WDT, 304 WDT,
305 RTC1, 305 RTC1,
306 QDEC, 306 QDEC,
307 COMP_LPCOMP, 307 COMP_LPCOMP,
308 SWI0_EGU0, 308 EGU0_SWI0,
309 SWI1_EGU1, 309 EGU1_SWI1,
310 SWI2_EGU2, 310 EGU2_SWI2,
311 SWI3_EGU3, 311 EGU3_SWI3,
312 SWI4_EGU4, 312 EGU4_SWI4,
313 SWI5_EGU5, 313 EGU5_SWI5,
314 TIMER3, 314 TIMER3,
315 TIMER4, 315 TIMER4,
316 PWM0, 316 PWM0,
@@ -318,8 +318,8 @@ embassy_hal_internal::interrupt_mod!(
318 MWU, 318 MWU,
319 PWM1, 319 PWM1,
320 PWM2, 320 PWM2,
321 SPIM2_SPIS2_SPI2, 321 SPI2,
322 RTC2, 322 RTC2,
323 FPU,
324 I2S, 323 I2S,
324 FPU,
325); 325);
diff --git a/embassy-nrf/src/chips/nrf52833.rs b/embassy-nrf/src/chips/nrf52833.rs
index 6d70b763f..a6273452a 100644
--- a/embassy-nrf/src/chips/nrf52833.rs
+++ b/embassy-nrf/src/chips/nrf52833.rs
@@ -185,23 +185,23 @@ embassy_hal_internal::peripherals! {
185 185
186impl_usb!(USBD, USBD, USBD); 186impl_usb!(USBD, USBD, USBD);
187 187
188impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); 188impl_uarte!(UARTE0, UARTE0, UARTE0);
189impl_uarte!(UARTE1, UARTE1, UARTE1); 189impl_uarte!(UARTE1, UARTE1, UARTE1);
190 190
191impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 191impl_spim!(TWISPI0, SPIM0, TWISPI0);
192impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 192impl_spim!(TWISPI1, SPIM1, TWISPI1);
193impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2); 193impl_spim!(SPI2, SPIM2, SPI2);
194impl_spim!(SPI3, SPIM3, SPIM3); 194impl_spim!(SPI3, SPIM3, SPIM3);
195 195
196impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 196impl_spis!(TWISPI0, SPIS0, TWISPI0);
197impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 197impl_spis!(TWISPI1, SPIS1, TWISPI1);
198impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2); 198impl_spis!(SPI2, SPIS2, SPI2);
199 199
200impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 200impl_twim!(TWISPI0, TWIM0, TWISPI0);
201impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 201impl_twim!(TWISPI1, TWIM1, TWISPI1);
202 202
203impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 203impl_twis!(TWISPI0, TWIS0, TWISPI0);
204impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 204impl_twis!(TWISPI1, TWIS1, TWISPI1);
205 205
206impl_pwm!(PWM0, PWM0, PWM0); 206impl_pwm!(PWM0, PWM0, PWM0);
207impl_pwm!(PWM1, PWM1, PWM1); 207impl_pwm!(PWM1, PWM1, PWM1);
@@ -319,19 +319,19 @@ impl_i2s!(I2S, I2S, I2S);
319 319
320impl_radio!(RADIO, RADIO, RADIO); 320impl_radio!(RADIO, RADIO, RADIO);
321 321
322impl_egu!(EGU0, EGU0, SWI0_EGU0); 322impl_egu!(EGU0, EGU0, EGU0_SWI0);
323impl_egu!(EGU1, EGU1, SWI1_EGU1); 323impl_egu!(EGU1, EGU1, EGU1_SWI1);
324impl_egu!(EGU2, EGU2, SWI2_EGU2); 324impl_egu!(EGU2, EGU2, EGU2_SWI2);
325impl_egu!(EGU3, EGU3, SWI3_EGU3); 325impl_egu!(EGU3, EGU3, EGU3_SWI3);
326impl_egu!(EGU4, EGU4, SWI4_EGU4); 326impl_egu!(EGU4, EGU4, EGU4_SWI4);
327impl_egu!(EGU5, EGU5, SWI5_EGU5); 327impl_egu!(EGU5, EGU5, EGU5_SWI5);
328 328
329embassy_hal_internal::interrupt_mod!( 329embassy_hal_internal::interrupt_mod!(
330 POWER_CLOCK, 330 CLOCK_POWER,
331 RADIO, 331 RADIO,
332 UARTE0_UART0, 332 UARTE0,
333 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, 333 TWISPI0,
334 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, 334 TWISPI1,
335 NFCT, 335 NFCT,
336 GPIOTE, 336 GPIOTE,
337 SAADC, 337 SAADC,
@@ -342,17 +342,17 @@ embassy_hal_internal::interrupt_mod!(
342 TEMP, 342 TEMP,
343 RNG, 343 RNG,
344 ECB, 344 ECB,
345 CCM_AAR, 345 AAR_CCM,
346 WDT, 346 WDT,
347 RTC1, 347 RTC1,
348 QDEC, 348 QDEC,
349 COMP_LPCOMP, 349 COMP_LPCOMP,
350 SWI0_EGU0, 350 EGU0_SWI0,
351 SWI1_EGU1, 351 EGU1_SWI1,
352 SWI2_EGU2, 352 EGU2_SWI2,
353 SWI3_EGU3, 353 EGU3_SWI3,
354 SWI4_EGU4, 354 EGU4_SWI4,
355 SWI5_EGU5, 355 EGU5_SWI5,
356 TIMER3, 356 TIMER3,
357 TIMER4, 357 TIMER4,
358 PWM0, 358 PWM0,
@@ -360,12 +360,12 @@ embassy_hal_internal::interrupt_mod!(
360 MWU, 360 MWU,
361 PWM1, 361 PWM1,
362 PWM2, 362 PWM2,
363 SPIM2_SPIS2_SPI2, 363 SPI2,
364 RTC2, 364 RTC2,
365 I2S,
365 FPU, 366 FPU,
366 USBD, 367 USBD,
367 UARTE1, 368 UARTE1,
368 PWM3, 369 PWM3,
369 SPIM3, 370 SPIM3,
370 I2S,
371); 371);
diff --git a/embassy-nrf/src/chips/nrf52840.rs b/embassy-nrf/src/chips/nrf52840.rs
index b6afbf213..fb341afd5 100644
--- a/embassy-nrf/src/chips/nrf52840.rs
+++ b/embassy-nrf/src/chips/nrf52840.rs
@@ -188,23 +188,23 @@ embassy_hal_internal::peripherals! {
188 188
189impl_usb!(USBD, USBD, USBD); 189impl_usb!(USBD, USBD, USBD);
190 190
191impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); 191impl_uarte!(UARTE0, UARTE0, UARTE0);
192impl_uarte!(UARTE1, UARTE1, UARTE1); 192impl_uarte!(UARTE1, UARTE1, UARTE1);
193 193
194impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 194impl_spim!(TWISPI0, SPIM0, TWISPI0);
195impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 195impl_spim!(TWISPI1, SPIM1, TWISPI1);
196impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2); 196impl_spim!(SPI2, SPIM2, SPI2);
197impl_spim!(SPI3, SPIM3, SPIM3); 197impl_spim!(SPI3, SPIM3, SPIM3);
198 198
199impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 199impl_spis!(TWISPI0, SPIS0, TWISPI0);
200impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 200impl_spis!(TWISPI1, SPIS1, TWISPI1);
201impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2); 201impl_spis!(SPI2, SPIS2, SPI2);
202 202
203impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 203impl_twim!(TWISPI0, TWIM0, TWISPI0);
204impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 204impl_twim!(TWISPI1, TWIM1, TWISPI1);
205 205
206impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); 206impl_twis!(TWISPI0, TWIS0, TWISPI0);
207impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); 207impl_twis!(TWISPI1, TWIS1, TWISPI1);
208 208
209impl_pwm!(PWM0, PWM0, PWM0); 209impl_pwm!(PWM0, PWM0, PWM0);
210impl_pwm!(PWM1, PWM1, PWM1); 210impl_pwm!(PWM1, PWM1, PWM1);
@@ -324,19 +324,19 @@ impl_i2s!(I2S, I2S, I2S);
324 324
325impl_radio!(RADIO, RADIO, RADIO); 325impl_radio!(RADIO, RADIO, RADIO);
326 326
327impl_egu!(EGU0, EGU0, SWI0_EGU0); 327impl_egu!(EGU0, EGU0, EGU0_SWI0);
328impl_egu!(EGU1, EGU1, SWI1_EGU1); 328impl_egu!(EGU1, EGU1, EGU1_SWI1);
329impl_egu!(EGU2, EGU2, SWI2_EGU2); 329impl_egu!(EGU2, EGU2, EGU2_SWI2);
330impl_egu!(EGU3, EGU3, SWI3_EGU3); 330impl_egu!(EGU3, EGU3, EGU3_SWI3);
331impl_egu!(EGU4, EGU4, SWI4_EGU4); 331impl_egu!(EGU4, EGU4, EGU4_SWI4);
332impl_egu!(EGU5, EGU5, SWI5_EGU5); 332impl_egu!(EGU5, EGU5, EGU5_SWI5);
333 333
334embassy_hal_internal::interrupt_mod!( 334embassy_hal_internal::interrupt_mod!(
335 POWER_CLOCK, 335 CLOCK_POWER,
336 RADIO, 336 RADIO,
337 UARTE0_UART0, 337 UARTE0,
338 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, 338 TWISPI0,
339 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, 339 TWISPI1,
340 NFCT, 340 NFCT,
341 GPIOTE, 341 GPIOTE,
342 SAADC, 342 SAADC,
@@ -347,17 +347,17 @@ embassy_hal_internal::interrupt_mod!(
347 TEMP, 347 TEMP,
348 RNG, 348 RNG,
349 ECB, 349 ECB,
350 CCM_AAR, 350 AAR_CCM,
351 WDT, 351 WDT,
352 RTC1, 352 RTC1,
353 QDEC, 353 QDEC,
354 COMP_LPCOMP, 354 COMP_LPCOMP,
355 SWI0_EGU0, 355 EGU0_SWI0,
356 SWI1_EGU1, 356 EGU1_SWI1,
357 SWI2_EGU2, 357 EGU2_SWI2,
358 SWI3_EGU3, 358 EGU3_SWI3,
359 SWI4_EGU4, 359 EGU4_SWI4,
360 SWI5_EGU5, 360 EGU5_SWI5,
361 TIMER3, 361 TIMER3,
362 TIMER4, 362 TIMER4,
363 PWM0, 363 PWM0,
@@ -365,8 +365,9 @@ embassy_hal_internal::interrupt_mod!(
365 MWU, 365 MWU,
366 PWM1, 366 PWM1,
367 PWM2, 367 PWM2,
368 SPIM2_SPIS2_SPI2, 368 SPI2,
369 RTC2, 369 RTC2,
370 I2S,
370 FPU, 371 FPU,
371 USBD, 372 USBD,
372 UARTE1, 373 UARTE1,
@@ -374,5 +375,4 @@ embassy_hal_internal::interrupt_mod!(
374 CRYPTOCELL, 375 CRYPTOCELL,
375 PWM3, 376 PWM3,
376 SPIM3, 377 SPIM3,
377 I2S,
378); 378);
diff --git a/embassy-nrf/src/chips/nrf5340_app.rs b/embassy-nrf/src/chips/nrf5340_app.rs
index d7846b094..6dc64fb4f 100644
--- a/embassy-nrf/src/chips/nrf5340_app.rs
+++ b/embassy-nrf/src/chips/nrf5340_app.rs
@@ -2,229 +2,158 @@
2#[allow(unused_imports)] 2#[allow(unused_imports)]
3#[rustfmt::skip] 3#[rustfmt::skip]
4pub mod pac { 4pub mod pac {
5 // The nRF5340 has a secure and non-secure (NS) mode. 5 pub use nrf_pac::*;
6 // To avoid cfg spam, we remove _ns or _s suffixes here.
7
8 #[cfg(feature="rt")]
9 pub use nrf_pac::NVIC_PRIO_BITS;
10 pub use nrf_pac::{common, shared};
11
12 #[cfg(feature="rt")]
13 #[doc(no_inline)]
14 pub use nrf_pac::interrupt;
15 6
7 #[cfg(feature = "_ns")]
16 #[doc(no_inline)] 8 #[doc(no_inline)]
17 pub use nrf_pac::{ 9 pub use nrf_pac::{
18 Interrupt, 10 CLOCK_NS as CLOCK,
19 11 COMP_NS as COMP,
20 cache_s as cache, 12 CTRLAP_NS as CTRLAP,
21 cachedata_s as cachedata, 13 DCNF_NS as DCNF,
22 cacheinfo_s as cacheinfo, 14 DPPIC_NS as DPPIC,
23 clock_ns as clock, 15 EGU0_NS as EGU0,
24 comp_ns as comp, 16 EGU1_NS as EGU1,
25 cryptocell_s as cryptocell, 17 EGU2_NS as EGU2,
26 cti_s as cti, 18 EGU3_NS as EGU3,
27 ctrlap_ns as ctrlap, 19 EGU4_NS as EGU4,
28 dcnf_ns as dcnf, 20 EGU5_NS as EGU5,
29 dppic_ns as dppic, 21 FPU_NS as FPU,
30 egu_ns as egu, 22 GPIOTE1_NS as GPIOTE1,
31 ficr_s as ficr, 23 I2S0_NS as I2S0,
32 fpu_ns as fpu, 24 IPC_NS as IPC,
33 gpiote_s as gpiote, 25 KMU_NS as KMU,
34 i2s_ns as i2s, 26 LPCOMP_NS as LPCOMP,
35 ipc_ns as ipc, 27 MUTEX_NS as MUTEX,
36 kmu_ns as kmu, 28 NFCT_NS as NFCT,
37 lpcomp_ns as lpcomp, 29 NVMC_NS as NVMC,
38 mutex_ns as mutex, 30 OSCILLATORS_NS as OSCILLATORS,
39 nfct_ns as nfct, 31 P0_NS as P0,
40 nvmc_ns as nvmc, 32 P1_NS as P1,
41 oscillators_ns as oscillators, 33 PDM0_NS as PDM0,
42 gpio_ns as gpio, 34 POWER_NS as POWER,
43 pdm_ns as pdm, 35 PWM0_NS as PWM0,
44 power_ns as power, 36 PWM1_NS as PWM1,
45 pwm_ns as pwm, 37 PWM2_NS as PWM2,
46 qdec_ns as qdec, 38 PWM3_NS as PWM3,
47 qspi_ns as qspi, 39 QDEC0_NS as QDEC0,
48 regulators_ns as regulators, 40 QDEC1_NS as QDEC1,
49 reset_ns as reset, 41 QSPI_NS as QSPI,
50 rtc_ns as rtc, 42 REGULATORS_NS as REGULATORS,
51 saadc_ns as saadc, 43 RESET_NS as RESET,
52 spim_ns as spim, 44 RTC0_NS as RTC0,
53 spis_ns as spis, 45 RTC1_NS as RTC1,
54 spu_s as spu, 46 SAADC_NS as SAADC,
55 tad_s as tad, 47 SPIM0_NS as SPIM0,
56 timer_ns as timer, 48 SPIM1_NS as SPIM1,
57 twim_ns as twim, 49 SPIM2_NS as SPIM2,
58 twis_ns as twis, 50 SPIM3_NS as SPIM3,
59 uarte_ns as uarte, 51 SPIM4_NS as SPIM4,
60 uicr_s as uicr, 52 SPIS0_NS as SPIS0,
61 usbd_ns as usbd, 53 SPIS1_NS as SPIS1,
62 usbregulator_ns as usbregulator, 54 SPIS2_NS as SPIS2,
63 vmc_ns as vmc, 55 SPIS3_NS as SPIS3,
64 wdt_ns as wdt, 56 TIMER0_NS as TIMER0,
57 TIMER1_NS as TIMER1,
58 TIMER2_NS as TIMER2,
59 TWIM0_NS as TWIM0,
60 TWIM1_NS as TWIM1,
61 TWIM2_NS as TWIM2,
62 TWIM3_NS as TWIM3,
63 TWIS0_NS as TWIS0,
64 TWIS1_NS as TWIS1,
65 TWIS2_NS as TWIS2,
66 TWIS3_NS as TWIS3,
67 UARTE0_NS as UARTE0,
68 UARTE1_NS as UARTE1,
69 UARTE2_NS as UARTE2,
70 UARTE3_NS as UARTE3,
71 USBD_NS as USBD,
72 USBREGULATOR_NS as USBREGULATOR,
73 VMC_NS as VMC,
74 WDT0_NS as WDT0,
75 WDT1_NS as WDT1,
65 }; 76 };
66
67 /// Non-Secure mode (NS) peripherals
68 pub mod ns {
69 #[cfg(feature = "nrf5340-app-ns")]
70 #[doc(no_inline)]
71 pub use nrf_pac::{
72 CLOCK_NS as CLOCK,
73 COMP_NS as COMP,
74 CTRLAP_NS as CTRLAP,
75 DCNF_NS as DCNF,
76 DPPIC_NS as DPPIC,
77 EGU0_NS as EGU0,
78 EGU1_NS as EGU1,
79 EGU2_NS as EGU2,
80 EGU3_NS as EGU3,
81 EGU4_NS as EGU4,
82 EGU5_NS as EGU5,
83 FPU_NS as FPU,
84 GPIOTE1_NS as GPIOTE1,
85 I2S0_NS as I2S0,
86 IPC_NS as IPC,
87 KMU_NS as KMU,
88 LPCOMP_NS as LPCOMP,
89 MUTEX_NS as MUTEX,
90 NFCT_NS as NFCT,
91 NVMC_NS as NVMC,
92 OSCILLATORS_NS as OSCILLATORS,
93 P0_NS as P0,
94 P1_NS as P1,
95 PDM0_NS as PDM0,
96 POWER_NS as POWER,
97 PWM0_NS as PWM0,
98 PWM1_NS as PWM1,
99 PWM2_NS as PWM2,
100 PWM3_NS as PWM3,
101 QDEC0_NS as QDEC0,
102 QDEC1_NS as QDEC1,
103 QSPI_NS as QSPI,
104 REGULATORS_NS as REGULATORS,
105 RESET_NS as RESET,
106 RTC0_NS as RTC0,
107 RTC1_NS as RTC1,
108 SAADC_NS as SAADC,
109 SPIM0_NS as SPIM0,
110 SPIM1_NS as SPIM1,
111 SPIM2_NS as SPIM2,
112 SPIM3_NS as SPIM3,
113 SPIM4_NS as SPIM4,
114 SPIS0_NS as SPIS0,
115 SPIS1_NS as SPIS1,
116 SPIS2_NS as SPIS2,
117 SPIS3_NS as SPIS3,
118 TIMER0_NS as TIMER0,
119 TIMER1_NS as TIMER1,
120 TIMER2_NS as TIMER2,
121 TWIM0_NS as TWIM0,
122 TWIM1_NS as TWIM1,
123 TWIM2_NS as TWIM2,
124 TWIM3_NS as TWIM3,
125 TWIS0_NS as TWIS0,
126 TWIS1_NS as TWIS1,
127 TWIS2_NS as TWIS2,
128 TWIS3_NS as TWIS3,
129 UARTE0_NS as UARTE0,
130 UARTE1_NS as UARTE1,
131 UARTE2_NS as UARTE2,
132 UARTE3_NS as UARTE3,
133 USBD_NS as USBD,
134 USBREGULATOR_NS as USBREGULATOR,
135 VMC_NS as VMC,
136 WDT0_NS as WDT0,
137 WDT1_NS as WDT1,
138 };
139 }
140
141 /// Secure mode (S) peripherals
142 pub mod s {
143 #[cfg(feature = "nrf5340-app-s")]
144 #[doc(no_inline)]
145 pub use nrf_pac::{
146 CACHEDATA_S as CACHEDATA,
147 CACHEINFO_S as CACHEINFO,
148 CACHE_S as CACHE,
149 CLOCK_S as CLOCK,
150 COMP_S as COMP,
151 CRYPTOCELL_S as CRYPTOCELL,
152 CTI_S as CTI,
153 CTRLAP_S as CTRLAP,
154 DCNF_S as DCNF,
155 DPPIC_S as DPPIC,
156 EGU0_S as EGU0,
157 EGU1_S as EGU1,
158 EGU2_S as EGU2,
159 EGU3_S as EGU3,
160 EGU4_S as EGU4,
161 EGU5_S as EGU5,
162 FICR_S as FICR,
163 FPU_S as FPU,
164 GPIOTE0_S as GPIOTE0,
165 I2S0_S as I2S0,
166 IPC_S as IPC,
167 KMU_S as KMU,
168 LPCOMP_S as LPCOMP,
169 MUTEX_S as MUTEX,
170 NFCT_S as NFCT,
171 NVMC_S as NVMC,
172 OSCILLATORS_S as OSCILLATORS,
173 P0_S as P0,
174 P1_S as P1,
175 PDM0_S as PDM0,
176 POWER_S as POWER,
177 PWM0_S as PWM0,
178 PWM1_S as PWM1,
179 PWM2_S as PWM2,
180 PWM3_S as PWM3,
181 QDEC0_S as QDEC0,
182 QDEC1_S as QDEC1,
183 QSPI_S as QSPI,
184 REGULATORS_S as REGULATORS,
185 RESET_S as RESET,
186 RTC0_S as RTC0,
187 RTC1_S as RTC1,
188 SAADC_S as SAADC,
189 SPIM0_S as SPIM0,
190 SPIM1_S as SPIM1,
191 SPIM2_S as SPIM2,
192 SPIM3_S as SPIM3,
193 SPIM4_S as SPIM4,
194 SPIS0_S as SPIS0,
195 SPIS1_S as SPIS1,
196 SPIS2_S as SPIS2,
197 SPIS3_S as SPIS3,
198 SPU_S as SPU,
199 TAD_S as TAD,
200 TIMER0_S as TIMER0,
201 TIMER1_S as TIMER1,
202 TIMER2_S as TIMER2,
203 TWIM0_S as TWIM0,
204 TWIM1_S as TWIM1,
205 TWIM2_S as TWIM2,
206 TWIM3_S as TWIM3,
207 TWIS0_S as TWIS0,
208 TWIS1_S as TWIS1,
209 TWIS2_S as TWIS2,
210 TWIS3_S as TWIS3,
211 UARTE0_S as UARTE0,
212 UARTE1_S as UARTE1,
213 UARTE2_S as UARTE2,
214 UARTE3_S as UARTE3,
215 UICR_S as UICR,
216 USBD_S as USBD,
217 USBREGULATOR_S as USBREGULATOR,
218 VMC_S as VMC,
219 WDT0_S as WDT0,
220 WDT1_S as WDT1,
221 };
222 }
223 77
224 #[cfg(feature = "_ns")]
225 pub use ns::*;
226 #[cfg(feature = "_s")] 78 #[cfg(feature = "_s")]
227 pub use s::*; 79 #[doc(no_inline)]
80 pub use nrf_pac::{
81 CACHEDATA_S as CACHEDATA,
82 CACHEINFO_S as CACHEINFO,
83 CACHE_S as CACHE,
84 CLOCK_S as CLOCK,
85 COMP_S as COMP,
86 CRYPTOCELL_S as CRYPTOCELL,
87 CTI_S as CTI,
88 CTRLAP_S as CTRLAP,
89 DCNF_S as DCNF,
90 DPPIC_S as DPPIC,
91 EGU0_S as EGU0,
92 EGU1_S as EGU1,
93 EGU2_S as EGU2,
94 EGU3_S as EGU3,
95 EGU4_S as EGU4,
96 EGU5_S as EGU5,
97 FICR_S as FICR,
98 FPU_S as FPU,
99 GPIOTE0_S as GPIOTE0,
100 I2S0_S as I2S0,
101 IPC_S as IPC,
102 KMU_S as KMU,
103 LPCOMP_S as LPCOMP,
104 MUTEX_S as MUTEX,
105 NFCT_S as NFCT,
106 NVMC_S as NVMC,
107 OSCILLATORS_S as OSCILLATORS,
108 P0_S as P0,
109 P1_S as P1,
110 PDM0_S as PDM0,
111 POWER_S as POWER,
112 PWM0_S as PWM0,
113 PWM1_S as PWM1,
114 PWM2_S as PWM2,
115 PWM3_S as PWM3,
116 QDEC0_S as QDEC0,
117 QDEC1_S as QDEC1,
118 QSPI_S as QSPI,
119 REGULATORS_S as REGULATORS,
120 RESET_S as RESET,
121 RTC0_S as RTC0,
122 RTC1_S as RTC1,
123 SAADC_S as SAADC,
124 SPIM0_S as SPIM0,
125 SPIM1_S as SPIM1,
126 SPIM2_S as SPIM2,
127 SPIM3_S as SPIM3,
128 SPIM4_S as SPIM4,
129 SPIS0_S as SPIS0,
130 SPIS1_S as SPIS1,
131 SPIS2_S as SPIS2,
132 SPIS3_S as SPIS3,
133 SPU_S as SPU,
134 TAD_S as TAD,
135 TIMER0_S as TIMER0,
136 TIMER1_S as TIMER1,
137 TIMER2_S as TIMER2,
138 TWIM0_S as TWIM0,
139 TWIM1_S as TWIM1,
140 TWIM2_S as TWIM2,
141 TWIM3_S as TWIM3,
142 TWIS0_S as TWIS0,
143 TWIS1_S as TWIS1,
144 TWIS2_S as TWIS2,
145 TWIS3_S as TWIS3,
146 UARTE0_S as UARTE0,
147 UARTE1_S as UARTE1,
148 UARTE2_S as UARTE2,
149 UARTE3_S as UARTE3,
150 UICR_S as UICR,
151 USBD_S as USBD,
152 USBREGULATOR_S as USBREGULATOR,
153 VMC_S as VMC,
154 WDT0_S as WDT0,
155 WDT1_S as WDT1,
156 };
228} 157}
229 158
230/// The maximum buffer size that the EasyDMA can send/recv in one operation. 159/// The maximum buffer size that the EasyDMA can send/recv in one operation.
diff --git a/embassy-nrf/src/chips/nrf5340_net.rs b/embassy-nrf/src/chips/nrf5340_net.rs
index 00ff5fea6..6c6ac3fbb 100644
--- a/embassy-nrf/src/chips/nrf5340_net.rs
+++ b/embassy-nrf/src/chips/nrf5340_net.rs
@@ -2,55 +2,10 @@
2#[allow(unused_imports)] 2#[allow(unused_imports)]
3#[rustfmt::skip] 3#[rustfmt::skip]
4pub mod pac { 4pub mod pac {
5 // The nRF5340 has a secure and non-secure (NS) mode. 5 pub use nrf_pac::*;
6 // To avoid cfg spam, we remove _ns or _s suffixes here.
7
8 #[cfg(feature="rt")]
9 pub use nrf_pac::NVIC_PRIO_BITS;
10 pub use nrf_pac::{common, shared};
11
12 #[cfg(feature="rt")]
13 #[doc(no_inline)]
14 pub use nrf_pac::interrupt;
15 6
16 #[doc(no_inline)] 7 #[doc(no_inline)]
17 pub use nrf_pac::{ 8 pub use nrf_pac::{
18 Interrupt,
19
20 aar_ns as aar,
21 acl_ns as acl,
22 appmutex_ns as appmutex,
23 ccm_ns as ccm,
24 clock_ns as clock,
25 cti_ns as cti,
26 ctrlap_ns as ctrlap,
27 dcnf_ns as dcnf,
28 dppic_ns as dppic,
29 ecb_ns as ecb,
30 egu_ns as egu,
31 ficr_ns as ficr,
32 gpiote_ns as gpiote,
33 ipc_ns as ipc,
34 nvmc_ns as nvmc,
35 gpio_ns as gpio,
36 power_ns as power,
37 radio_ns as radio,
38 reset_ns as reset,
39 rng_ns as rng,
40 rtc_ns as rtc,
41 spim_ns as spim,
42 spis_ns as spis,
43 swi_ns as swi,
44 temp_ns as temp,
45 timer_ns as timer,
46 twim_ns as twim,
47 twis_ns as twis,
48 uarte_ns as uarte,
49 uicr_ns as uicr,
50 vmc_ns as vmc,
51 vreqctrl_ns as vreqctrl,
52 wdt_ns as wdt,
53
54 AAR_NS as AAR, 9 AAR_NS as AAR,
55 ACL_NS as ACL, 10 ACL_NS as ACL,
56 APPMUTEX_NS as APPMUTEX, 11 APPMUTEX_NS as APPMUTEX,
@@ -93,7 +48,6 @@ pub mod pac {
93 VREQCTRL_NS as VREQCTRL, 48 VREQCTRL_NS as VREQCTRL,
94 WDT_NS as WDT, 49 WDT_NS as WDT,
95 }; 50 };
96
97} 51}
98 52
99/// The maximum buffer size that the EasyDMA can send/recv in one operation. 53/// The maximum buffer size that the EasyDMA can send/recv in one operation.
diff --git a/embassy-nrf/src/chips/nrf9120.rs b/embassy-nrf/src/chips/nrf9120.rs
index b89570dcd..b02b8c6d8 100644
--- a/embassy-nrf/src/chips/nrf9120.rs
+++ b/embassy-nrf/src/chips/nrf9120.rs
@@ -2,179 +2,124 @@
2#[allow(unused_imports)] 2#[allow(unused_imports)]
3#[rustfmt::skip] 3#[rustfmt::skip]
4pub mod pac { 4pub mod pac {
5 // The nRF9120 has a secure and non-secure (NS) mode. 5 pub use nrf_pac::*;
6 // To avoid cfg spam, we remove _ns or _s suffixes here.
7
8 #[cfg(feature="rt")]
9 pub use nrf_pac::NVIC_PRIO_BITS;
10 pub use nrf_pac::{common, shared};
11
12 #[cfg(feature="rt")]
13 #[doc(no_inline)]
14 pub use nrf_pac::interrupt;
15 6
7 #[cfg(feature = "_ns")]
16 #[doc(no_inline)] 8 #[doc(no_inline)]
17 pub use nrf_pac::{ 9 pub use nrf_pac::{
18 Interrupt, 10 CLOCK_NS as CLOCK,
19 11 DPPIC_NS as DPPIC,
20 cc_host_rgf_s as cc_host_rgf, 12 EGU0_NS as EGU0,
21 clock_ns as clock, 13 EGU1_NS as EGU1,
22 cryptocell_s as cryptocell, 14 EGU2_NS as EGU2,
23 ctrl_ap_peri_s as ctrl_ap_peri, 15 EGU3_NS as EGU3,
24 dppic_ns as dppic, 16 EGU4_NS as EGU4,
25 egu_ns as egu, 17 EGU5_NS as EGU5,
26 ficr_s as ficr, 18 FPU_NS as FPU,
27 fpu_ns as fpu, 19 GPIOTE1_NS as GPIOTE1,
28 gpiote_s as gpiote, 20 I2S_NS as I2S,
29 i2s_ns as i2s, 21 IPC_NS as IPC,
30 ipc_ns as ipc, 22 KMU_NS as KMU,
31 kmu_ns as kmu, 23 NVMC_NS as NVMC,
32 nvmc_ns as nvmc, 24 P0_NS as P0,
33 gpio_ns as gpio, 25 PDM_NS as PDM,
34 pdm_ns as pdm, 26 POWER_NS as POWER,
35 power_ns as power, 27 PWM0_NS as PWM0,
36 pwm_ns as pwm, 28 PWM1_NS as PWM1,
37 regulators_ns as regulators, 29 PWM2_NS as PWM2,
38 rtc_ns as rtc, 30 PWM3_NS as PWM3,
39 saadc_ns as saadc, 31 REGULATORS_NS as REGULATORS,
40 spim_ns as spim, 32 RTC0_NS as RTC0,
41 spis_ns as spis, 33 RTC1_NS as RTC1,
42 spu_s as spu, 34 SAADC_NS as SAADC,
43 tad_s as tad, 35 SPIM0_NS as SPIM0,
44 timer_ns as timer, 36 SPIM1_NS as SPIM1,
45 twim_ns as twim, 37 SPIM2_NS as SPIM2,
46 twis_ns as twis, 38 SPIM3_NS as SPIM3,
47 uarte_ns as uarte, 39 SPIS0_NS as SPIS0,
48 uicr_s as uicr, 40 SPIS1_NS as SPIS1,
49 vmc_ns as vmc, 41 SPIS2_NS as SPIS2,
50 wdt_ns as wdt, 42 SPIS3_NS as SPIS3,
43 TIMER0_NS as TIMER0,
44 TIMER1_NS as TIMER1,
45 TIMER2_NS as TIMER2,
46 TWIM0_NS as TWIM0,
47 TWIM1_NS as TWIM1,
48 TWIM2_NS as TWIM2,
49 TWIM3_NS as TWIM3,
50 TWIS0_NS as TWIS0,
51 TWIS1_NS as TWIS1,
52 TWIS2_NS as TWIS2,
53 TWIS3_NS as TWIS3,
54 UARTE0_NS as UARTE0,
55 UARTE1_NS as UARTE1,
56 UARTE2_NS as UARTE2,
57 UARTE3_NS as UARTE3,
58 VMC_NS as VMC,
59 WDT_NS as WDT,
51 }; 60 };
52
53 /// Non-Secure mode (NS) peripherals
54 pub mod ns {
55 #[doc(no_inline)]
56 pub use nrf_pac::{
57 CLOCK_NS as CLOCK,
58 DPPIC_NS as DPPIC,
59 EGU0_NS as EGU0,
60 EGU1_NS as EGU1,
61 EGU2_NS as EGU2,
62 EGU3_NS as EGU3,
63 EGU4_NS as EGU4,
64 EGU5_NS as EGU5,
65 FPU_NS as FPU,
66 GPIOTE1_NS as GPIOTE1,
67 I2S_NS as I2S,
68 IPC_NS as IPC,
69 KMU_NS as KMU,
70 NVMC_NS as NVMC,
71 P0_NS as P0,
72 PDM_NS as PDM,
73 POWER_NS as POWER,
74 PWM0_NS as PWM0,
75 PWM1_NS as PWM1,
76 PWM2_NS as PWM2,
77 PWM3_NS as PWM3,
78 REGULATORS_NS as REGULATORS,
79 RTC0_NS as RTC0,
80 RTC1_NS as RTC1,
81 SAADC_NS as SAADC,
82 SPIM0_NS as SPIM0,
83 SPIM1_NS as SPIM1,
84 SPIM2_NS as SPIM2,
85 SPIM3_NS as SPIM3,
86 SPIS0_NS as SPIS0,
87 SPIS1_NS as SPIS1,
88 SPIS2_NS as SPIS2,
89 SPIS3_NS as SPIS3,
90 TIMER0_NS as TIMER0,
91 TIMER1_NS as TIMER1,
92 TIMER2_NS as TIMER2,
93 TWIM0_NS as TWIM0,
94 TWIM1_NS as TWIM1,
95 TWIM2_NS as TWIM2,
96 TWIM3_NS as TWIM3,
97 TWIS0_NS as TWIS0,
98 TWIS1_NS as TWIS1,
99 TWIS2_NS as TWIS2,
100 TWIS3_NS as TWIS3,
101 UARTE0_NS as UARTE0,
102 UARTE1_NS as UARTE1,
103 UARTE2_NS as UARTE2,
104 UARTE3_NS as UARTE3,
105 VMC_NS as VMC,
106 WDT_NS as WDT,
107 };
108 }
109
110 /// Secure mode (S) peripherals
111 pub mod s {
112 #[doc(no_inline)]
113 pub use nrf_pac::{
114 CC_HOST_RGF_S as CC_HOST_RGF,
115 CLOCK_S as CLOCK,
116 CRYPTOCELL_S as CRYPTOCELL,
117 CTRL_AP_PERI_S as CTRL_AP_PERI,
118 DPPIC_S as DPPIC,
119 EGU0_S as EGU0,
120 EGU1_S as EGU1,
121 EGU2_S as EGU2,
122 EGU3_S as EGU3,
123 EGU4_S as EGU4,
124 EGU5_S as EGU5,
125 FICR_S as FICR,
126 FPU_NS as FPU,
127 GPIOTE0_S as GPIOTE0,
128 I2S_S as I2S,
129 IPC_S as IPC,
130 KMU_S as KMU,
131 NVMC_S as NVMC,
132 P0_S as P0,
133 PDM_S as PDM,
134 POWER_S as POWER,
135 PWM0_S as PWM0,
136 PWM1_S as PWM1,
137 PWM2_S as PWM2,
138 PWM3_S as PWM3,
139 REGULATORS_S as REGULATORS,
140 RTC0_S as RTC0,
141 RTC1_S as RTC1,
142 SAADC_S as SAADC,
143 SPIM0_S as SPIM0,
144 SPIM1_S as SPIM1,
145 SPIM2_S as SPIM2,
146 SPIM3_S as SPIM3,
147 SPIS0_S as SPIS0,
148 SPIS1_S as SPIS1,
149 SPIS2_S as SPIS2,
150 SPIS3_S as SPIS3,
151 SPU_S as SPU,
152 TAD_S as TAD,
153 TIMER0_S as TIMER0,
154 TIMER1_S as TIMER1,
155 TIMER2_S as TIMER2,
156 TWIM0_S as TWIM0,
157 TWIM1_S as TWIM1,
158 TWIM2_S as TWIM2,
159 TWIM3_S as TWIM3,
160 TWIS0_S as TWIS0,
161 TWIS1_S as TWIS1,
162 TWIS2_S as TWIS2,
163 TWIS3_S as TWIS3,
164 UARTE0_S as UARTE0,
165 UARTE1_S as UARTE1,
166 UARTE2_S as UARTE2,
167 UARTE3_S as UARTE3,
168 UICR_S as UICR,
169 VMC_S as VMC,
170 WDT_S as WDT,
171 };
172 }
173 61
174 #[cfg(feature = "_ns")]
175 pub use ns::*;
176 #[cfg(feature = "_s")] 62 #[cfg(feature = "_s")]
177 pub use s::*; 63 #[doc(no_inline)]
64 pub use nrf_pac::{
65 CC_HOST_RGF_S as CC_HOST_RGF,
66 CLOCK_S as CLOCK,
67 CRYPTOCELL_S as CRYPTOCELL,
68 CTRL_AP_PERI_S as CTRL_AP_PERI,
69 DPPIC_S as DPPIC,
70 EGU0_S as EGU0,
71 EGU1_S as EGU1,
72 EGU2_S as EGU2,
73 EGU3_S as EGU3,
74 EGU4_S as EGU4,
75 EGU5_S as EGU5,
76 FICR_S as FICR,
77 FPU_NS as FPU,
78 GPIOTE0_S as GPIOTE0,
79 I2S_S as I2S,
80 IPC_S as IPC,
81 KMU_S as KMU,
82 NVMC_S as NVMC,
83 P0_S as P0,
84 PDM_S as PDM,
85 POWER_S as POWER,
86 PWM0_S as PWM0,
87 PWM1_S as PWM1,
88 PWM2_S as PWM2,
89 PWM3_S as PWM3,
90 REGULATORS_S as REGULATORS,
91 RTC0_S as RTC0,
92 RTC1_S as RTC1,
93 SAADC_S as SAADC,
94 SPIM0_S as SPIM0,
95 SPIM1_S as SPIM1,
96 SPIM2_S as SPIM2,
97 SPIM3_S as SPIM3,
98 SPIS0_S as SPIS0,
99 SPIS1_S as SPIS1,
100 SPIS2_S as SPIS2,
101 SPIS3_S as SPIS3,
102 SPU_S as SPU,
103 TAD_S as TAD,
104 TIMER0_S as TIMER0,
105 TIMER1_S as TIMER1,
106 TIMER2_S as TIMER2,
107 TWIM0_S as TWIM0,
108 TWIM1_S as TWIM1,
109 TWIM2_S as TWIM2,
110 TWIM3_S as TWIM3,
111 TWIS0_S as TWIS0,
112 TWIS1_S as TWIS1,
113 TWIS2_S as TWIS2,
114 TWIS3_S as TWIS3,
115 UARTE0_S as UARTE0,
116 UARTE1_S as UARTE1,
117 UARTE2_S as UARTE2,
118 UARTE3_S as UARTE3,
119 UICR_S as UICR,
120 VMC_S as VMC,
121 WDT_S as WDT,
122 };
178} 123}
179 124
180/// The maximum buffer size that the EasyDMA can send/recv in one operation. 125/// The maximum buffer size that the EasyDMA can send/recv in one operation.
@@ -295,30 +240,30 @@ embassy_hal_internal::peripherals! {
295 EGU5, 240 EGU5,
296} 241}
297 242
298impl_uarte!(SERIAL0, UARTE0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); 243impl_uarte!(SERIAL0, UARTE0, SERIAL0);
299impl_uarte!(SERIAL1, UARTE1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); 244impl_uarte!(SERIAL1, UARTE1, SERIAL1);
300impl_uarte!(SERIAL2, UARTE2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); 245impl_uarte!(SERIAL2, UARTE2, SERIAL2);
301impl_uarte!(SERIAL3, UARTE3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); 246impl_uarte!(SERIAL3, UARTE3, SERIAL3);
302 247
303impl_spim!(SERIAL0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); 248impl_spim!(SERIAL0, SPIM0, SERIAL0);
304impl_spim!(SERIAL1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); 249impl_spim!(SERIAL1, SPIM1, SERIAL1);
305impl_spim!(SERIAL2, SPIM2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); 250impl_spim!(SERIAL2, SPIM2, SERIAL2);
306impl_spim!(SERIAL3, SPIM3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); 251impl_spim!(SERIAL3, SPIM3, SERIAL3);
307 252
308impl_spis!(SERIAL0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); 253impl_spis!(SERIAL0, SPIS0, SERIAL0);
309impl_spis!(SERIAL1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); 254impl_spis!(SERIAL1, SPIS1, SERIAL1);
310impl_spis!(SERIAL2, SPIS2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); 255impl_spis!(SERIAL2, SPIS2, SERIAL2);
311impl_spis!(SERIAL3, SPIS3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); 256impl_spis!(SERIAL3, SPIS3, SERIAL3);
312 257
313impl_twim!(SERIAL0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); 258impl_twim!(SERIAL0, TWIM0, SERIAL0);
314impl_twim!(SERIAL1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); 259impl_twim!(SERIAL1, TWIM1, SERIAL1);
315impl_twim!(SERIAL2, TWIM2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); 260impl_twim!(SERIAL2, TWIM2, SERIAL2);
316impl_twim!(SERIAL3, TWIM3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); 261impl_twim!(SERIAL3, TWIM3, SERIAL3);
317 262
318impl_twis!(SERIAL0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); 263impl_twis!(SERIAL0, TWIS0, SERIAL0);
319impl_twis!(SERIAL1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); 264impl_twis!(SERIAL1, TWIS1, SERIAL1);
320impl_twis!(SERIAL2, TWIS2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); 265impl_twis!(SERIAL2, TWIS2, SERIAL2);
321impl_twis!(SERIAL3, TWIS3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); 266impl_twis!(SERIAL3, TWIS3, SERIAL3);
322 267
323impl_pwm!(PWM0, PWM0, PWM0); 268impl_pwm!(PWM0, PWM0, PWM0);
324impl_pwm!(PWM1, PWM1, PWM1); 269impl_pwm!(PWM1, PWM1, PWM1);
@@ -400,10 +345,10 @@ impl_egu!(EGU5, EGU5, EGU5);
400embassy_hal_internal::interrupt_mod!( 345embassy_hal_internal::interrupt_mod!(
401 SPU, 346 SPU,
402 CLOCK_POWER, 347 CLOCK_POWER,
403 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0, 348 SERIAL0,
404 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1, 349 SERIAL1,
405 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2, 350 SERIAL2,
406 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3, 351 SERIAL3,
407 GPIOTE0, 352 GPIOTE0,
408 SAADC, 353 SAADC,
409 TIMER0, 354 TIMER0,
@@ -421,8 +366,8 @@ embassy_hal_internal::interrupt_mod!(
421 PWM0, 366 PWM0,
422 PWM1, 367 PWM1,
423 PWM2, 368 PWM2,
424 PDM,
425 PWM3, 369 PWM3,
370 PDM,
426 I2S, 371 I2S,
427 IPC, 372 IPC,
428 FPU, 373 FPU,
diff --git a/embassy-nrf/src/chips/nrf9160.rs b/embassy-nrf/src/chips/nrf9160.rs
index dba3d1ef5..b0981e3b5 100644
--- a/embassy-nrf/src/chips/nrf9160.rs
+++ b/embassy-nrf/src/chips/nrf9160.rs
@@ -2,179 +2,124 @@
2#[allow(unused_imports)] 2#[allow(unused_imports)]
3#[rustfmt::skip] 3#[rustfmt::skip]
4pub mod pac { 4pub mod pac {
5 // The nRF9160 has a secure and non-secure (NS) mode. 5 pub use nrf_pac::*;
6 // To avoid cfg spam, we remove _ns or _s suffixes here.
7
8 #[cfg(feature="rt")]
9 pub use nrf_pac::NVIC_PRIO_BITS;
10 pub use nrf_pac::{common, shared};
11
12 #[cfg(feature="rt")]
13 #[doc(no_inline)]
14 pub use nrf_pac::interrupt;
15 6
7 #[cfg(feature = "_ns")]
16 #[doc(no_inline)] 8 #[doc(no_inline)]
17 pub use nrf_pac::{ 9 pub use nrf_pac::{
18 Interrupt, 10 CLOCK_NS as CLOCK,
19 11 DPPIC_NS as DPPIC,
20 cc_host_rgf_s as cc_host_rgf, 12 EGU0_NS as EGU0,
21 clock_ns as clock, 13 EGU1_NS as EGU1,
22 cryptocell_s as cryptocell, 14 EGU2_NS as EGU2,
23 ctrl_ap_peri_s as ctrl_ap_peri, 15 EGU3_NS as EGU3,
24 dppic_ns as dppic, 16 EGU4_NS as EGU4,
25 egu_ns as egu, 17 EGU5_NS as EGU5,
26 ficr_s as ficr, 18 FPU_NS as FPU,
27 fpu_ns as fpu, 19 GPIOTE1_NS as GPIOTE1,
28 gpiote_s as gpiote, 20 I2S_NS as I2S,
29 i2s_ns as i2s, 21 IPC_NS as IPC,
30 ipc_ns as ipc, 22 KMU_NS as KMU,
31 kmu_ns as kmu, 23 NVMC_NS as NVMC,
32 nvmc_ns as nvmc, 24 P0_NS as P0,
33 gpio_ns as gpio, 25 PDM_NS as PDM,
34 pdm_ns as pdm, 26 POWER_NS as POWER,
35 power_ns as power, 27 PWM0_NS as PWM0,
36 pwm_ns as pwm, 28 PWM1_NS as PWM1,
37 regulators_ns as regulators, 29 PWM2_NS as PWM2,
38 rtc_ns as rtc, 30 PWM3_NS as PWM3,
39 saadc_ns as saadc, 31 REGULATORS_NS as REGULATORS,
40 spim_ns as spim, 32 RTC0_NS as RTC0,
41 spis_ns as spis, 33 RTC1_NS as RTC1,
42 spu_s as spu, 34 SAADC_NS as SAADC,
43 tad_s as tad, 35 SPIM0_NS as SPIM0,
44 timer_ns as timer, 36 SPIM1_NS as SPIM1,
45 twim_ns as twim, 37 SPIM2_NS as SPIM2,
46 twis_ns as twis, 38 SPIM3_NS as SPIM3,
47 uarte_ns as uarte, 39 SPIS0_NS as SPIS0,
48 uicr_s as uicr, 40 SPIS1_NS as SPIS1,
49 vmc_ns as vmc, 41 SPIS2_NS as SPIS2,
50 wdt_ns as wdt, 42 SPIS3_NS as SPIS3,
43 TIMER0_NS as TIMER0,
44 TIMER1_NS as TIMER1,
45 TIMER2_NS as TIMER2,
46 TWIM0_NS as TWIM0,
47 TWIM1_NS as TWIM1,
48 TWIM2_NS as TWIM2,
49 TWIM3_NS as TWIM3,
50 TWIS0_NS as TWIS0,
51 TWIS1_NS as TWIS1,
52 TWIS2_NS as TWIS2,
53 TWIS3_NS as TWIS3,
54 UARTE0_NS as UARTE0,
55 UARTE1_NS as UARTE1,
56 UARTE2_NS as UARTE2,
57 UARTE3_NS as UARTE3,
58 VMC_NS as VMC,
59 WDT_NS as WDT,
51 }; 60 };
52
53 /// Non-Secure mode (NS) peripherals
54 pub mod ns {
55 #[doc(no_inline)]
56 pub use nrf_pac::{
57 CLOCK_NS as CLOCK,
58 DPPIC_NS as DPPIC,
59 EGU0_NS as EGU0,
60 EGU1_NS as EGU1,
61 EGU2_NS as EGU2,
62 EGU3_NS as EGU3,
63 EGU4_NS as EGU4,
64 EGU5_NS as EGU5,
65 FPU_NS as FPU,
66 GPIOTE1_NS as GPIOTE1,
67 I2S_NS as I2S,
68 IPC_NS as IPC,
69 KMU_NS as KMU,
70 NVMC_NS as NVMC,
71 P0_NS as P0,
72 PDM_NS as PDM,
73 POWER_NS as POWER,
74 PWM0_NS as PWM0,
75 PWM1_NS as PWM1,
76 PWM2_NS as PWM2,
77 PWM3_NS as PWM3,
78 REGULATORS_NS as REGULATORS,
79 RTC0_NS as RTC0,
80 RTC1_NS as RTC1,
81 SAADC_NS as SAADC,
82 SPIM0_NS as SPIM0,
83 SPIM1_NS as SPIM1,
84 SPIM2_NS as SPIM2,
85 SPIM3_NS as SPIM3,
86 SPIS0_NS as SPIS0,
87 SPIS1_NS as SPIS1,
88 SPIS2_NS as SPIS2,
89 SPIS3_NS as SPIS3,
90 TIMER0_NS as TIMER0,
91 TIMER1_NS as TIMER1,
92 TIMER2_NS as TIMER2,
93 TWIM0_NS as TWIM0,
94 TWIM1_NS as TWIM1,
95 TWIM2_NS as TWIM2,
96 TWIM3_NS as TWIM3,
97 TWIS0_NS as TWIS0,
98 TWIS1_NS as TWIS1,
99 TWIS2_NS as TWIS2,
100 TWIS3_NS as TWIS3,
101 UARTE0_NS as UARTE0,
102 UARTE1_NS as UARTE1,
103 UARTE2_NS as UARTE2,
104 UARTE3_NS as UARTE3,
105 VMC_NS as VMC,
106 WDT_NS as WDT,
107 };
108 }
109
110 /// Secure mode (S) peripherals
111 pub mod s {
112 #[doc(no_inline)]
113 pub use nrf_pac::{
114 CC_HOST_RGF_S as CC_HOST_RGF,
115 CLOCK_S as CLOCK,
116 CRYPTOCELL_S as CRYPTOCELL,
117 CTRL_AP_PERI_S as CTRL_AP_PERI,
118 DPPIC_S as DPPIC,
119 EGU0_S as EGU0,
120 EGU1_S as EGU1,
121 EGU2_S as EGU2,
122 EGU3_S as EGU3,
123 EGU4_S as EGU4,
124 EGU5_S as EGU5,
125 FICR_S as FICR,
126 FPU_S as FPU,
127 GPIOTE0_S as GPIOTE0,
128 I2S_S as I2S,
129 IPC_S as IPC,
130 KMU_S as KMU,
131 NVMC_S as NVMC,
132 P0_S as P0,
133 PDM_S as PDM,
134 POWER_S as POWER,
135 PWM0_S as PWM0,
136 PWM1_S as PWM1,
137 PWM2_S as PWM2,
138 PWM3_S as PWM3,
139 REGULATORS_S as REGULATORS,
140 RTC0_S as RTC0,
141 RTC1_S as RTC1,
142 SAADC_S as SAADC,
143 SPIM0_S as SPIM0,
144 SPIM1_S as SPIM1,
145 SPIM2_S as SPIM2,
146 SPIM3_S as SPIM3,
147 SPIS0_S as SPIS0,
148 SPIS1_S as SPIS1,
149 SPIS2_S as SPIS2,
150 SPIS3_S as SPIS3,
151 SPU_S as SPU,
152 TAD_S as TAD,
153 TIMER0_S as TIMER0,
154 TIMER1_S as TIMER1,
155 TIMER2_S as TIMER2,
156 TWIM0_S as TWIM0,
157 TWIM1_S as TWIM1,
158 TWIM2_S as TWIM2,
159 TWIM3_S as TWIM3,
160 TWIS0_S as TWIS0,
161 TWIS1_S as TWIS1,
162 TWIS2_S as TWIS2,
163 TWIS3_S as TWIS3,
164 UARTE0_S as UARTE0,
165 UARTE1_S as UARTE1,
166 UARTE2_S as UARTE2,
167 UARTE3_S as UARTE3,
168 UICR_S as UICR,
169 VMC_S as VMC,
170 WDT_S as WDT,
171 };
172 }
173 61
174 #[cfg(feature = "_ns")]
175 pub use ns::*;
176 #[cfg(feature = "_s")] 62 #[cfg(feature = "_s")]
177 pub use s::*; 63 #[doc(no_inline)]
64 pub use nrf_pac::{
65 CC_HOST_RGF_S as CC_HOST_RGF,
66 CLOCK_S as CLOCK,
67 CRYPTOCELL_S as CRYPTOCELL,
68 CTRL_AP_PERI_S as CTRL_AP_PERI,
69 DPPIC_S as DPPIC,
70 EGU0_S as EGU0,
71 EGU1_S as EGU1,
72 EGU2_S as EGU2,
73 EGU3_S as EGU3,
74 EGU4_S as EGU4,
75 EGU5_S as EGU5,
76 FICR_S as FICR,
77 FPU_S as FPU,
78 GPIOTE0_S as GPIOTE0,
79 I2S_S as I2S,
80 IPC_S as IPC,
81 KMU_S as KMU,
82 NVMC_S as NVMC,
83 P0_S as P0,
84 PDM_S as PDM,
85 POWER_S as POWER,
86 PWM0_S as PWM0,
87 PWM1_S as PWM1,
88 PWM2_S as PWM2,
89 PWM3_S as PWM3,
90 REGULATORS_S as REGULATORS,
91 RTC0_S as RTC0,
92 RTC1_S as RTC1,
93 SAADC_S as SAADC,
94 SPIM0_S as SPIM0,
95 SPIM1_S as SPIM1,
96 SPIM2_S as SPIM2,
97 SPIM3_S as SPIM3,
98 SPIS0_S as SPIS0,
99 SPIS1_S as SPIS1,
100 SPIS2_S as SPIS2,
101 SPIS3_S as SPIS3,
102 SPU_S as SPU,
103 TAD_S as TAD,
104 TIMER0_S as TIMER0,
105 TIMER1_S as TIMER1,
106 TIMER2_S as TIMER2,
107 TWIM0_S as TWIM0,
108 TWIM1_S as TWIM1,
109 TWIM2_S as TWIM2,
110 TWIM3_S as TWIM3,
111 TWIS0_S as TWIS0,
112 TWIS1_S as TWIS1,
113 TWIS2_S as TWIS2,
114 TWIS3_S as TWIS3,
115 UARTE0_S as UARTE0,
116 UARTE1_S as UARTE1,
117 UARTE2_S as UARTE2,
118 UARTE3_S as UARTE3,
119 UICR_S as UICR,
120 VMC_S as VMC,
121 WDT_S as WDT,
122 };
178} 123}
179 124
180/// The maximum buffer size that the EasyDMA can send/recv in one operation. 125/// The maximum buffer size that the EasyDMA can send/recv in one operation.
@@ -295,30 +240,30 @@ embassy_hal_internal::peripherals! {
295 EGU5, 240 EGU5,
296} 241}
297 242
298impl_uarte!(SERIAL0, UARTE0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); 243impl_uarte!(SERIAL0, UARTE0, SERIAL0);
299impl_uarte!(SERIAL1, UARTE1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); 244impl_uarte!(SERIAL1, UARTE1, SERIAL1);
300impl_uarte!(SERIAL2, UARTE2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); 245impl_uarte!(SERIAL2, UARTE2, SERIAL2);
301impl_uarte!(SERIAL3, UARTE3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); 246impl_uarte!(SERIAL3, UARTE3, SERIAL3);
302 247
303impl_spim!(SERIAL0, SPIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); 248impl_spim!(SERIAL0, SPIM0, SERIAL0);
304impl_spim!(SERIAL1, SPIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); 249impl_spim!(SERIAL1, SPIM1, SERIAL1);
305impl_spim!(SERIAL2, SPIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); 250impl_spim!(SERIAL2, SPIM2, SERIAL2);
306impl_spim!(SERIAL3, SPIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); 251impl_spim!(SERIAL3, SPIM3, SERIAL3);
307 252
308impl_spis!(SERIAL0, SPIS0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); 253impl_spis!(SERIAL0, SPIS0, SERIAL0);
309impl_spis!(SERIAL1, SPIS1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); 254impl_spis!(SERIAL1, SPIS1, SERIAL1);
310impl_spis!(SERIAL2, SPIS2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); 255impl_spis!(SERIAL2, SPIS2, SERIAL2);
311impl_spis!(SERIAL3, SPIS3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); 256impl_spis!(SERIAL3, SPIS3, SERIAL3);
312 257
313impl_twim!(SERIAL0, TWIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); 258impl_twim!(SERIAL0, TWIM0, SERIAL0);
314impl_twim!(SERIAL1, TWIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); 259impl_twim!(SERIAL1, TWIM1, SERIAL1);
315impl_twim!(SERIAL2, TWIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); 260impl_twim!(SERIAL2, TWIM2, SERIAL2);
316impl_twim!(SERIAL3, TWIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); 261impl_twim!(SERIAL3, TWIM3, SERIAL3);
317 262
318impl_twis!(SERIAL0, TWIS0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); 263impl_twis!(SERIAL0, TWIS0, SERIAL0);
319impl_twis!(SERIAL1, TWIS1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); 264impl_twis!(SERIAL1, TWIS1, SERIAL1);
320impl_twis!(SERIAL2, TWIS2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); 265impl_twis!(SERIAL2, TWIS2, SERIAL2);
321impl_twis!(SERIAL3, TWIS3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); 266impl_twis!(SERIAL3, TWIS3, SERIAL3);
322 267
323impl_pwm!(PWM0, PWM0, PWM0); 268impl_pwm!(PWM0, PWM0, PWM0);
324impl_pwm!(PWM1, PWM1, PWM1); 269impl_pwm!(PWM1, PWM1, PWM1);
@@ -400,10 +345,10 @@ impl_egu!(EGU5, EGU5, EGU5);
400embassy_hal_internal::interrupt_mod!( 345embassy_hal_internal::interrupt_mod!(
401 SPU, 346 SPU,
402 CLOCK_POWER, 347 CLOCK_POWER,
403 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0, 348 SERIAL0,
404 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1, 349 SERIAL1,
405 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2, 350 SERIAL2,
406 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3, 351 SERIAL3,
407 GPIOTE0, 352 GPIOTE0,
408 SAADC, 353 SAADC,
409 TIMER0, 354 TIMER0,
@@ -421,8 +366,8 @@ embassy_hal_internal::interrupt_mod!(
421 PWM0, 366 PWM0,
422 PWM1, 367 PWM1,
423 PWM2, 368 PWM2,
424 PDM,
425 PWM3, 369 PWM3,
370 PDM,
426 I2S, 371 I2S,
427 IPC, 372 IPC,
428 FPU, 373 FPU,
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 430b6fae7..8167b44f3 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -170,7 +170,7 @@ mod chip;
170/// 170///
171/// bind_interrupts!(struct Irqs { 171/// bind_interrupts!(struct Irqs {
172/// SPIM3 => spim::InterruptHandler<peripherals::SPI3>; 172/// SPIM3 => spim::InterruptHandler<peripherals::SPI3>;
173/// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => twim::InterruptHandler<peripherals::TWISPI0>; 173/// TWISPI0 => twim::InterruptHandler<peripherals::TWISPI0>;
174/// }); 174/// });
175/// ``` 175/// ```
176 176
diff --git a/embassy-nrf/src/time_driver.rs b/embassy-nrf/src/time_driver.rs
index e39c4ed52..b6492ac97 100644
--- a/embassy-nrf/src/time_driver.rs
+++ b/embassy-nrf/src/time_driver.rs
@@ -132,7 +132,7 @@ impl RtcDriver {
132 132
133 r.intenset().write(|w| { 133 r.intenset().write(|w| {
134 w.set_ovrflw(true); 134 w.set_ovrflw(true);
135 w.set_compare3(true); 135 w.set_compare(3, true);
136 }); 136 });
137 137
138 r.tasks_clear().write_value(1); 138 r.tasks_clear().write_value(1);
diff --git a/embassy-nrf/src/usb/vbus_detect.rs b/embassy-nrf/src/usb/vbus_detect.rs
index 7f816a5ad..bdc088dcb 100644
--- a/embassy-nrf/src/usb/vbus_detect.rs
+++ b/embassy-nrf/src/usb/vbus_detect.rs
@@ -29,14 +29,14 @@ pub trait VbusDetect {
29} 29}
30 30
31#[cfg(not(feature = "_nrf5340"))] 31#[cfg(not(feature = "_nrf5340"))]
32type UsbRegIrq = interrupt::typelevel::POWER_CLOCK; 32type UsbRegIrq = interrupt::typelevel::CLOCK_POWER;
33#[cfg(feature = "_nrf5340")] 33#[cfg(feature = "_nrf5340")]
34type UsbRegIrq = interrupt::typelevel::USBREGULATOR; 34type UsbRegIrq = interrupt::typelevel::USBREGULATOR;
35 35
36#[cfg(not(feature = "_nrf5340"))] 36#[cfg(not(feature = "_nrf5340"))]
37const USB_REG_PERI: pac::power::Power = pac::POWER; 37const USB_REG_PERI: pac::power::Power = pac::POWER;
38#[cfg(feature = "_nrf5340")] 38#[cfg(feature = "_nrf5340")]
39const USB_REG_PERI: pac::usbregulator::Usbregulator = pac::USBREGULATOR; 39const USB_REG_PERI: pac::usbreg::Usbreg = pac::USBREGULATOR;
40 40
41/// Interrupt handler. 41/// Interrupt handler.
42pub struct InterruptHandler { 42pub struct InterruptHandler {