lpc55: pint rewritten

1 files changed, 33 insertions, 64 deletions

diff --git a/embassy-nxp/src/pint.rs b/embassy-nxp/src/pint.rs
index ff414b4e6..e594aaa6a 100644
--- a/embassy-nxp/src/pint.rs
+++ b/embassy-nxp/src/pint.rs
@@ -5,10 +5,11 @@ use core::pin::Pin as FuturePin;
 use core::task::{Context, Poll};
 
 use critical_section::Mutex;
+use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_sync::waitqueue::AtomicWaker;
 
-use crate::gpio::{self, inputmux_reg, pint_reg, syscon_reg, AnyPin, Level, SealedPin};
-use crate::pac::interrupt;
+use crate::gpio::{self, AnyPin, Level, SealedPin};
+use crate::pac::{interrupt, INPUTMUX, PINT, SYSCON};
 use crate::Peri;
 
 struct PinInterrupt {
@@ -88,18 +89,18 @@ enum InterruptOn {
 }
 
 pub(crate) fn init() {
-    syscon_reg().ahbclkctrl0.modify(|_, w| w.pint().enable());
+    SYSCON.ahbclkctrl0().modify(|w| w.set_pint(true));
 
     // Enable interrupts
     unsafe {
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT0);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT1);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT2);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT3);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT4);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT5);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT6);
-        crate::pac::NVIC::unmask(crate::pac::Interrupt::PIN_INT7);
+        interrupt::PIN_INT0.enable();
+        interrupt::PIN_INT1.enable();
+        interrupt::PIN_INT2.enable();
+        interrupt::PIN_INT3.enable();
+        interrupt::PIN_INT4.enable();
+        interrupt::PIN_INT5.enable();
+        interrupt::PIN_INT6.enable();
+        interrupt::PIN_INT7.enable();
     };
 
     info!("Pin interrupts initialized");
@@ -119,24 +120,19 @@ impl<'d> InputFuture<'d> {
         let interrupt_number = next_available_interrupt()?;
 
         // Clear interrupt, just in case
-        pint_reg()
-            .rise
-            .write(|w| unsafe { w.rdet().bits(1 << interrupt_number) });
-        pint_reg()
-            .fall
-            .write(|w| unsafe { w.fdet().bits(1 << interrupt_number) });
+        PINT.rise().write(|w| w.set_rdet(1 << interrupt_number));
+        PINT.fall().write(|w| w.set_fdet(1 << interrupt_number));
 
         // Enable input multiplexing on pin interrupt register 0 for pin (32*bank + pin_number)
-        inputmux_reg().pintsel[interrupt_number]
-            .write(|w| unsafe { w.intpin().bits(32 * pin.pin_bank() as u8 + pin.pin_number()) });
+        INPUTMUX
+            .pintsel(interrupt_number as usize)
+            .write(|w| w.set_intpin(32 * pin.pin_bank() as u8 + pin.pin_number()));
 
         match interrupt_on {
             InterruptOn::Level(level) => {
                 // Set pin interrupt register to edge sensitive or level sensitive
                 // 0 = edge sensitive, 1 = level sensitive
-                pint_reg()
-                    .isel
-                    .modify(|r, w| unsafe { w.bits(r.bits() | (1 << interrupt_number)) });
+                PINT.isel().modify(|w| w.set_pmode(w.pmode() | (1 << interrupt_number)));
 
                 // Enable level interrupt.
                 //
@@ -144,63 +140,44 @@ impl<'d> InputFuture<'d> {
                 // is activated.
 
                 // 0 = no-op, 1 = enable
-                pint_reg()
-                    .sienr
-                    .write(|w| unsafe { w.setenrl().bits(1 << interrupt_number) });
+                PINT.sienr().write(|w| w.set_setenrl(1 << interrupt_number));
 
                 // Set active level
                 match level {
                     Level::Low => {
                         // 0 = no-op, 1 = select LOW
-                        pint_reg()
-                            .cienf
-                            .write(|w| unsafe { w.cenaf().bits(1 << interrupt_number) });
+                        PINT.cienf().write(|w| w.set_cenaf(1 << interrupt_number));
                     }
                     Level::High => {
                         // 0 = no-op, 1 = select HIGH
-                        pint_reg()
-                            .sienf
-                            .write(|w| unsafe { w.setenaf().bits(1 << interrupt_number) });
+                        PINT.sienf().write(|w| w.set_setenaf(1 << interrupt_number));
                     }
                 }
             }
             InterruptOn::Edge(edge) => {
                 // Set pin interrupt register to edge sensitive or level sensitive
                 // 0 = edge sensitive, 1 = level sensitive
-                pint_reg()
-                    .isel
-                    .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << interrupt_number)) });
+                PINT.isel()
+                    .modify(|w| w.set_pmode(w.pmode() & !(1 << interrupt_number)));
 
                 // Enable rising/falling edge detection
                 match edge {
                     Edge::Rising => {
                         // 0 = no-op, 1 = enable rising edge
-                        pint_reg()
-                            .sienr
-                            .write(|w| unsafe { w.setenrl().bits(1 << interrupt_number) });
+                        PINT.sienr().write(|w| w.set_setenrl(1 << interrupt_number));
                         // 0 = no-op, 1 = disable falling edge
-                        pint_reg()
-                            .cienf
-                            .write(|w| unsafe { w.cenaf().bits(1 << interrupt_number) });
+                        PINT.cienf().write(|w| w.set_cenaf(1 << interrupt_number));
                     }
                     Edge::Falling => {
                         // 0 = no-op, 1 = enable falling edge
-                        pint_reg()
-                            .sienf
-                            .write(|w| unsafe { w.setenaf().bits(1 << interrupt_number) });
+                        PINT.sienf().write(|w| w.set_setenaf(1 << interrupt_number));
                         // 0 = no-op, 1 = disable rising edge
-                        pint_reg()
-                            .cienr
-                            .write(|w| unsafe { w.cenrl().bits(1 << interrupt_number) });
+                        PINT.cienr().write(|w| w.set_cenrl(1 << interrupt_number));
                     }
                     Edge::Both => {
                         // 0 = no-op, 1 = enable
-                        pint_reg()
-                            .sienr
-                            .write(|w| unsafe { w.setenrl().bits(1 << interrupt_number) });
-                        pint_reg()
-                            .sienf
-                            .write(|w| unsafe { w.setenaf().bits(1 << interrupt_number) });
+                        PINT.sienr().write(|w| w.set_setenrl(1 << interrupt_number));
+                        PINT.sienf().write(|w| w.set_setenaf(1 << interrupt_number));
                     }
                 }
             }
@@ -239,12 +216,8 @@ impl<'d> Drop for InputFuture<'d> {
 
         // Disable pin interrupt
         // 0 = no-op, 1 = disable
-        pint_reg()
-            .cienr
-            .write(|w| unsafe { w.cenrl().bits(1 << interrupt_number) });
-        pint_reg()
-            .cienf
-            .write(|w| unsafe { w.cenaf().bits(1 << interrupt_number) });
+        PINT.cienr().write(|w| w.set_cenrl(1 << interrupt_number));
+        PINT.cienf().write(|w| w.set_cenaf(1 << interrupt_number));
 
         critical_section::with(|cs| {
             let mut pin_interrupts = PIN_INTERRUPTS.borrow(cs).borrow_mut();
@@ -277,12 +250,8 @@ impl<'d> Future for InputFuture<'d> {
 }
 
 fn handle_interrupt(interrupt_number: usize) {
-    pint_reg()
-        .rise
-        .write(|w| unsafe { w.rdet().bits(1 << interrupt_number) });
-    pint_reg()
-        .fall
-        .write(|w| unsafe { w.fdet().bits(1 << interrupt_number) });
+    PINT.rise().write(|w| w.set_rdet(1 << interrupt_number));
+    PINT.fall().write(|w| w.set_fdet(1 << interrupt_number));
 
     critical_section::with(|cs| {
         let mut pin_interrupts = PIN_INTERRUPTS.borrow(cs).borrow_mut();