Merge branch 'main' into rp2040-rtc-alarm

5 files changed, 690 insertions, 14 deletions

diff --git a/embassy-rp/src/pio_programs/i2s.rs b/embassy-rp/src/pio_programs/i2s.rs
index b967f0160..2382a3f9f 100644
--- a/embassy-rp/src/pio_programs/i2s.rs
+++ b/embassy-rp/src/pio_programs/i2s.rs
@@ -1,14 +1,106 @@
-//! Pio backed I2s output
+//! Pio backed I2s output and output drivers
 
 use fixed::traits::ToFixed;
 
 use crate::dma::{AnyChannel, Channel, Transfer};
+use crate::gpio::Pull;
 use crate::pio::{
     Common, Config, Direction, FifoJoin, Instance, LoadedProgram, PioPin, ShiftConfig, ShiftDirection, StateMachine,
 };
 use crate::Peri;
 
+/// This struct represents an i2s receiver & controller driver program
+pub struct PioI2sInProgram<'d, PIO: Instance> {
+    prg: LoadedProgram<'d, PIO>,
+}
+
+impl<'d, PIO: Instance> PioI2sInProgram<'d, PIO> {
+    /// Load the input program into the given pio
+    pub fn new(common: &mut Common<'d, PIO>) -> Self {
+        let prg = pio::pio_asm! {
+            ".side_set 2",
+            "   set x, 14               side 0b01",
+            "left_data:",
+            "   in pins, 1              side 0b00", // read one left-channel bit from SD
+            "   jmp x-- left_data       side 0b01",
+            "   in pins, 1              side 0b10", // ws changes 1 clock before MSB
+            "   set x, 14               side 0b11",
+            "right_data:",
+            "   in pins, 1             side 0b10",
+            "   jmp x-- right_data     side 0b11",
+            "   in pins, 1             side 0b00" // ws changes 1 clock before ms
+        };
+        let prg = common.load_program(&prg.program);
+        Self { prg }
+    }
+}
+
+/// Pio backed I2s input driver
+pub struct PioI2sIn<'d, P: Instance, const S: usize> {
+    dma: Peri<'d, AnyChannel>,
+    sm: StateMachine<'d, P, S>,
+}
+
+impl<'d, P: Instance, const S: usize> PioI2sIn<'d, P, S> {
+    /// Configure a state machine to act as both the controller (provider of SCK and WS) and receiver (of SD) for an I2S signal
+    pub fn new(
+        common: &mut Common<'d, P>,
+        mut sm: StateMachine<'d, P, S>,
+        dma: Peri<'d, impl Channel>,
+        // Whether or not to use the MCU's internal pull-down resistor, as the
+        // Pico 2 is known to have problems with the inbuilt pulldowns, many
+        // opt to just use an external pull down resistor to meet requirements of common
+        // i2s microphones such as the INMP441
+        data_pulldown: bool,
+        data_pin: Peri<'d, impl PioPin>,
+        bit_clock_pin: Peri<'d, impl PioPin>,
+        lr_clock_pin: Peri<'d, impl PioPin>,
+        sample_rate: u32,
+        bit_depth: u32,
+        channels: u32,
+        program: &PioI2sInProgram<'d, P>,
+    ) -> Self {
+        let mut data_pin = common.make_pio_pin(data_pin);
+        if data_pulldown {
+            data_pin.set_pull(Pull::Down);
+        }
+        let bit_clock_pin = common.make_pio_pin(bit_clock_pin);
+        let left_right_clock_pin = common.make_pio_pin(lr_clock_pin);
+
+        let cfg = {
+            let mut cfg = Config::default();
+            cfg.use_program(&program.prg, &[&bit_clock_pin, &left_right_clock_pin]);
+            cfg.set_in_pins(&[&data_pin]);
+            let clock_frequency = sample_rate * bit_depth * channels;
+            cfg.clock_divider = (crate::clocks::clk_sys_freq() as f64 / clock_frequency as f64 / 2.).to_fixed();
+            cfg.shift_in = ShiftConfig {
+                threshold: 32,
+                direction: ShiftDirection::Left,
+                auto_fill: true,
+            };
+            // join fifos to have twice the time to start the next dma transfer
+            cfg.fifo_join = FifoJoin::RxOnly; // both control signals are sent via side-setting
+            cfg
+        };
+        sm.set_config(&cfg);
+        sm.set_pin_dirs(Direction::In, &[&data_pin]);
+        sm.set_pin_dirs(Direction::Out, &[&left_right_clock_pin, &bit_clock_pin]);
+        sm.set_enable(true);
+
+        Self { dma: dma.into(), sm }
+    }
+
+    /// Return an in-prograss dma transfer future. Awaiting it will guarentee a complete transfer.
+    pub fn read<'b>(&'b mut self, buff: &'b mut [u32]) -> Transfer<'b, AnyChannel> {
+        self.sm.rx().dma_pull(self.dma.reborrow(), buff, false)
+    }
+}
+
 /// This struct represents an i2s output driver program
+///
+/// The sample bit-depth is set through scratch register `Y`.
+/// `Y` has to be set to sample bit-depth - 2.
+/// (14 = 16bit, 22 = 24bit, 30 = 32bit)
 pub struct PioI2sOutProgram<'d, PIO: Instance> {
     prg: LoadedProgram<'d, PIO>,
 }
@@ -17,17 +109,17 @@ impl<'d, PIO: Instance> PioI2sOutProgram<'d, PIO> {
     /// Load the program into the given pio
     pub fn new(common: &mut Common<'d, PIO>) -> Self {
         let prg = pio::pio_asm!(
-            ".side_set 2",
-            "    set x, 14          side 0b01", // side 0bWB - W = Word Clock, B = Bit Clock
+            ".side_set 2",                      // side 0bWB - W = Word Clock, B = Bit Clock
+            "    mov x, y           side 0b01", // y stores sample depth - 2 (14 = 16bit, 22 = 24bit, 30 = 32bit)
             "left_data:",
             "    out pins, 1        side 0b00",
             "    jmp x-- left_data  side 0b01",
-            "    out pins 1         side 0b10",
-            "    set x, 14          side 0b11",
+            "    out pins, 1        side 0b10",
+            "    mov x, y           side 0b11",
             "right_data:",
-            "    out pins 1         side 0b10",
+            "    out pins, 1         side 0b10",
             "    jmp x-- right_data side 0b11",
-            "    out pins 1         side 0b00",
+            "    out pins, 1         side 0b00",
         );
 
         let prg = common.load_program(&prg.program);
@@ -53,7 +145,6 @@ impl<'d, P: Instance, const S: usize> PioI2sOut<'d, P, S> {
         lr_clock_pin: Peri<'d, impl PioPin>,
         sample_rate: u32,
         bit_depth: u32,
-        channels: u32,
         program: &PioI2sOutProgram<'d, P>,
     ) -> Self {
         let data_pin = common.make_pio_pin(data_pin);
@@ -64,7 +155,7 @@ impl<'d, P: Instance, const S: usize> PioI2sOut<'d, P, S> {
             let mut cfg = Config::default();
             cfg.use_program(&program.prg, &[&bit_clock_pin, &left_right_clock_pin]);
             cfg.set_out_pins(&[&data_pin]);
-            let clock_frequency = sample_rate * bit_depth * channels;
+            let clock_frequency = sample_rate * bit_depth * 2;
             cfg.clock_divider = (crate::clocks::clk_sys_freq() as f64 / clock_frequency as f64 / 2.).to_fixed();
             cfg.shift_out = ShiftConfig {
                 threshold: 32,
@@ -78,6 +169,11 @@ impl<'d, P: Instance, const S: usize> PioI2sOut<'d, P, S> {
         sm.set_config(&cfg);
         sm.set_pin_dirs(Direction::Out, &[&data_pin, &left_right_clock_pin, &bit_clock_pin]);
 
+        // Set the `y` register up to configure the sample depth
+        // The SM counts down to 0 and uses one clock cycle to set up the counter,
+        // which results in bit_depth - 2 as register value.
+        unsafe { sm.set_y(bit_depth - 2) };
+
         sm.set_enable(true);
 
         Self { dma: dma.into(), sm }
diff --git a/embassy-rp/src/pio_programs/mod.rs b/embassy-rp/src/pio_programs/mod.rs
index 8eac328b3..d05ba3884 100644
--- a/embassy-rp/src/pio_programs/mod.rs
+++ b/embassy-rp/src/pio_programs/mod.rs
@@ -6,6 +6,7 @@ pub mod i2s;
 pub mod onewire;
 pub mod pwm;
 pub mod rotary_encoder;
+pub mod spi;
 pub mod stepper;
 pub mod uart;
 pub mod ws2812;
diff --git a/embassy-rp/src/pio_programs/onewire.rs b/embassy-rp/src/pio_programs/onewire.rs
index 287ddab41..980d0fe5f 100644
--- a/embassy-rp/src/pio_programs/onewire.rs
+++ b/embassy-rp/src/pio_programs/onewire.rs
@@ -52,7 +52,8 @@ impl<'a, PIO: Instance> PioOneWireProgram<'a, PIO> {
 
                     ; The low pulse was already done, we only need to delay and poll the bit in case we are reading
                     write_1:
-                        nop                     side 0 [( 6 / CLK) - 1]     ; Delay before sampling the input pin
+                        jmp y--, continue_1     side 0 [( 6 / CLK) - 1]     ; Delay before sampling input. Always decrement y
+                    continue_1:
                         in pins, 1              side 0 [(48 / CLK) - 1]     ; This writes the state of the pin into the ISR
                         ; Fallthrough
 
@@ -61,9 +62,24 @@ impl<'a, PIO: Instance> PioOneWireProgram<'a, PIO> {
                     .wrap_target
                         out x, 1                side 0 [(12 / CLK) - 1]     ; Stalls if no data available in TX FIFO and OSR
                         jmp x--, write_1        side 1 [( 6 / CLK) - 1]     ; Do the always low part of a bit, jump to write_1 if we want to write a 1 bit
-                        in null, 1              side 1 [(54 / CLK) - 1]     ; Do the remainder of the low part of a 0 bit
-                                                                            ; This writes 0 into the ISR so that the shift count stays in sync
+                        jmp y--, continue_0     side 1 [(48 / CLK) - 1]     ; Do the remainder of the low part of a 0 bit
+                        jmp pullup              side 1 [( 6 / CLK) - 1]     ; Remain low while jumping
+                    continue_0:
+                        in null, 1              side 1 [( 6 / CLK) - 1]     ; This writes 0 into the ISR so that the shift count stays in sync
                     .wrap
+
+                    ; Assume that strong pullup commands always have MSB (the last bit) = 0,
+                    ; since the rising edge can be used to start the operation.
+                    ; That's the case for DS18B20 (44h and 48h).
+                    pullup:
+                        set pins, 1             side 1[( 6 / CLK) - 1]      ; Drive pin high output immediately.
+                                                                            ; Strong pullup must be within 10us of rise.
+                        in null, 1              side 1[( 6 / CLK) - 1]      ; Keep ISR in sync. Must occur after the y--.
+                        out null, 8             side 1[( 6 / CLK) - 1]      ; Wait for write_bytes_pullup() delay to complete.
+                                                                            ; The delay is hundreds of ms, so done externally.
+                        set pins, 0             side 0[( 6 / CLK) - 1]      ; Back to open drain, pin low when driven
+                        in null, 8              side 1[( 6 / CLK) - 1]      ; Inform write_bytes_pullup() it's ready
+                        jmp next_bit            side 0[( 6 / CLK) - 1]      ; Continue
             "#
         );
 
@@ -98,6 +114,7 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
         let mut cfg = Config::default();
         cfg.use_program(&program.prg, &[&pin]);
         cfg.set_in_pins(&[&pin]);
+        cfg.set_set_pins(&[&pin]);
 
         let shift_cfg = ShiftConfig {
             auto_fill: true,
@@ -146,6 +163,19 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
 
     /// Write bytes to the onewire bus
     pub async fn write_bytes(&mut self, data: &[u8]) {
+        unsafe { self.sm.set_y(u32::MAX as u32) };
+        let (rx, tx) = self.sm.rx_tx();
+        for b in data {
+            tx.wait_push(*b as u32).await;
+
+            // Empty the buffer that is being filled with every write
+            let _ = rx.wait_pull().await;
+        }
+    }
+
+    /// Write bytes to the onewire bus, then apply a strong pullup
+    pub async fn write_bytes_pullup(&mut self, data: &[u8], pullup_time: embassy_time::Duration) {
+        unsafe { self.sm.set_y(data.len() as u32 * 8 - 1) };
         let (rx, tx) = self.sm.rx_tx();
         for b in data {
             tx.wait_push(*b as u32).await;
@@ -153,10 +183,19 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
             // Empty the buffer that is being filled with every write
             let _ = rx.wait_pull().await;
         }
+
+        // Perform the delay, usually hundreds of ms.
+        embassy_time::Timer::after(pullup_time).await;
+
+        // Signal that delay has completed
+        tx.wait_push(0 as u32).await;
+        // Wait until it's back at 0 low, open drain
+        let _ = rx.wait_pull().await;
     }
 
     /// Read bytes from the onewire bus
     pub async fn read_bytes(&mut self, data: &mut [u8]) {
+        unsafe { self.sm.set_y(u32::MAX as u32) };
         let (rx, tx) = self.sm.rx_tx();
         for b in data {
             // Write all 1's so that we can read what the device responds
diff --git a/embassy-rp/src/pio_programs/spi.rs b/embassy-rp/src/pio_programs/spi.rs
new file mode 100644
index 000000000..b10fc6628
--- /dev/null
+++ b/embassy-rp/src/pio_programs/spi.rs
@@ -0,0 +1,474 @@
+//! PIO backed SPi drivers
+
+use core::marker::PhantomData;
+
+use embassy_futures::join::join;
+use embassy_hal_internal::Peri;
+use embedded_hal_02::spi::{Phase, Polarity};
+use fixed::traits::ToFixed;
+use fixed::types::extra::U8;
+
+use crate::clocks::clk_sys_freq;
+use crate::dma::{AnyChannel, Channel};
+use crate::gpio::Level;
+use crate::pio::{Common, Direction, Instance, LoadedProgram, Pin, PioPin, ShiftDirection, StateMachine};
+use crate::spi::{Async, Blocking, Config, Mode};
+
+/// This struct represents an SPI program loaded into pio instruction memory.
+struct PioSpiProgram<'d, PIO: Instance> {
+    prg: LoadedProgram<'d, PIO>,
+    phase: Phase,
+}
+
+impl<'d, PIO: Instance> PioSpiProgram<'d, PIO> {
+    /// Load the spi program into the given pio
+    pub fn new(common: &mut Common<'d, PIO>, phase: Phase) -> Self {
+        // These PIO programs are taken straight from the datasheet (3.6.1 in
+        // RP2040 datasheet, 11.6.1 in RP2350 datasheet)
+
+        // Pin assignments:
+        // - SCK is side-set pin 0
+        // - MOSI is OUT pin 0
+        // - MISO is IN pin 0
+        //
+        // Auto-push and auto-pull must be enabled, and the serial frame size is set by
+        // configuring the push/pull threshold. Shift left/right is fine, but you must
+        // justify the data yourself. This is done most conveniently for frame sizes of
+        // 8 or 16 bits by using the narrow store replication and narrow load byte
+        // picking behavior of RP2040's IO fabric.
+
+        let prg = match phase {
+            Phase::CaptureOnFirstTransition => {
+                let prg = pio::pio_asm!(
+                    r#"
+                        .side_set 1
+
+                        ; Clock phase = 0: data is captured on the leading edge of each SCK pulse, and
+                        ; transitions on the trailing edge, or some time before the first leading edge.
+
+                        out pins, 1 side 0 [1] ; Stall here on empty (sideset proceeds even if
+                        in pins, 1  side 1 [1] ; instruction stalls, so we stall with SCK low)
+                    "#
+                );
+
+                common.load_program(&prg.program)
+            }
+            Phase::CaptureOnSecondTransition => {
+                let prg = pio::pio_asm!(
+                    r#"
+                        .side_set 1
+
+                        ; Clock phase = 1: data transitions on the leading edge of each SCK pulse, and
+                        ; is captured on the trailing edge.
+
+                        out x, 1    side 0     ; Stall here on empty (keep SCK de-asserted)
+                        mov pins, x side 1 [1] ; Output data, assert SCK (mov pins uses OUT mapping)
+                        in pins, 1  side 0     ; Input data, de-assert SCK
+                    "#
+                );
+
+                common.load_program(&prg.program)
+            }
+        };
+
+        Self { prg, phase }
+    }
+}
+
+/// PIO SPI errors.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+    // No errors for now
+}
+
+/// PIO based Spi driver.
+/// Unlike other PIO programs, the PIO SPI driver owns and holds a reference to
+/// the PIO memory it uses. This is so that it can be reconfigured at runtime if
+/// desired.
+pub struct Spi<'d, PIO: Instance, const SM: usize, M: Mode> {
+    sm: StateMachine<'d, PIO, SM>,
+    cfg: crate::pio::Config<'d, PIO>,
+    program: Option<PioSpiProgram<'d, PIO>>,
+    clk_pin: Pin<'d, PIO>,
+    tx_dma: Option<Peri<'d, AnyChannel>>,
+    rx_dma: Option<Peri<'d, AnyChannel>>,
+    phantom: PhantomData<M>,
+}
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> Spi<'d, PIO, SM, M> {
+    #[allow(clippy::too_many_arguments)]
+    fn new_inner(
+        pio: &mut Common<'d, PIO>,
+        mut sm: StateMachine<'d, PIO, SM>,
+        clk_pin: Peri<'d, impl PioPin>,
+        mosi_pin: Peri<'d, impl PioPin>,
+        miso_pin: Peri<'d, impl PioPin>,
+        tx_dma: Option<Peri<'d, AnyChannel>>,
+        rx_dma: Option<Peri<'d, AnyChannel>>,
+        config: Config,
+    ) -> Self {
+        let program = PioSpiProgram::new(pio, config.phase);
+
+        let mut clk_pin = pio.make_pio_pin(clk_pin);
+        let mosi_pin = pio.make_pio_pin(mosi_pin);
+        let miso_pin = pio.make_pio_pin(miso_pin);
+
+        if let Polarity::IdleHigh = config.polarity {
+            clk_pin.set_output_inversion(true);
+        } else {
+            clk_pin.set_output_inversion(false);
+        }
+
+        let mut cfg = crate::pio::Config::default();
+
+        cfg.use_program(&program.prg, &[&clk_pin]);
+        cfg.set_out_pins(&[&mosi_pin]);
+        cfg.set_in_pins(&[&miso_pin]);
+
+        cfg.shift_in.auto_fill = true;
+        cfg.shift_in.direction = ShiftDirection::Left;
+        cfg.shift_in.threshold = 8;
+
+        cfg.shift_out.auto_fill = true;
+        cfg.shift_out.direction = ShiftDirection::Left;
+        cfg.shift_out.threshold = 8;
+
+        cfg.clock_divider = calculate_clock_divider(config.frequency);
+
+        sm.set_config(&cfg);
+
+        sm.set_pins(Level::Low, &[&clk_pin, &mosi_pin]);
+        sm.set_pin_dirs(Direction::Out, &[&clk_pin, &mosi_pin]);
+        sm.set_pin_dirs(Direction::In, &[&miso_pin]);
+
+        sm.set_enable(true);
+
+        Self {
+            sm,
+            program: Some(program),
+            cfg,
+            clk_pin,
+            tx_dma,
+            rx_dma,
+            phantom: PhantomData,
+        }
+    }
+
+    fn blocking_read_u8(&mut self) -> Result<u8, Error> {
+        while self.sm.rx().empty() {}
+        let value = self.sm.rx().pull() as u8;
+
+        Ok(value)
+    }
+
+    fn blocking_write_u8(&mut self, v: u8) -> Result<(), Error> {
+        let value = u32::from_be_bytes([v, 0, 0, 0]);
+
+        while !self.sm.tx().try_push(value) {}
+
+        // need to clear here for flush to work correctly
+        self.sm.tx().stalled();
+
+        Ok(())
+    }
+
+    /// Read data from SPI blocking execution until done.
+    pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<(), Error> {
+        for v in data {
+            self.blocking_write_u8(0)?;
+            *v = self.blocking_read_u8()?;
+        }
+        self.flush()?;
+        Ok(())
+    }
+
+    /// Write data to SPI blocking execution until done.
+    pub fn blocking_write(&mut self, data: &[u8]) -> Result<(), Error> {
+        for v in data {
+            self.blocking_write_u8(*v)?;
+            let _ = self.blocking_read_u8()?;
+        }
+        self.flush()?;
+        Ok(())
+    }
+
+    /// Transfer data to SPI blocking execution until done.
+    pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
+        let len = read.len().max(write.len());
+        for i in 0..len {
+            let wb = write.get(i).copied().unwrap_or(0);
+            self.blocking_write_u8(wb)?;
+
+            let rb = self.blocking_read_u8()?;
+            if let Some(r) = read.get_mut(i) {
+                *r = rb;
+            }
+        }
+        self.flush()?;
+        Ok(())
+    }
+
+    /// Transfer data in place to SPI blocking execution until done.
+    pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
+        for v in data {
+            self.blocking_write_u8(*v)?;
+            *v = self.blocking_read_u8()?;
+        }
+        self.flush()?;
+        Ok(())
+    }
+
+    /// Block execution until SPI is done.
+    pub fn flush(&mut self) -> Result<(), Error> {
+        // Wait for all words in the FIFO to have been pulled by the SM
+        while !self.sm.tx().empty() {}
+
+        // Wait for last value to be written out to the wire
+        while !self.sm.tx().stalled() {}
+
+        Ok(())
+    }
+
+    /// Set SPI frequency.
+    pub fn set_frequency(&mut self, freq: u32) {
+        self.sm.set_enable(false);
+
+        let divider = calculate_clock_divider(freq);
+
+        // save into the config for later but dont use sm.set_config() since
+        // that operation is relatively more expensive than just setting the
+        // clock divider
+        self.cfg.clock_divider = divider;
+        self.sm.set_clock_divider(divider);
+
+        self.sm.set_enable(true);
+    }
+
+    /// Set SPI config.
+    ///
+    /// This operation will panic if the PIO program needs to be reloaded and
+    /// there is insufficient room. This is unlikely since the programs for each
+    /// phase only differ in size by a single instruction.
+    pub fn set_config(&mut self, pio: &mut Common<'d, PIO>, config: &Config) {
+        self.sm.set_enable(false);
+
+        self.cfg.clock_divider = calculate_clock_divider(config.frequency);
+
+        if let Polarity::IdleHigh = config.polarity {
+            self.clk_pin.set_output_inversion(true);
+        } else {
+            self.clk_pin.set_output_inversion(false);
+        }
+
+        if self.program.as_ref().unwrap().phase != config.phase {
+            let old_program = self.program.take().unwrap();
+
+            // SAFETY: the state machine is disabled while this happens
+            unsafe { pio.free_instr(old_program.prg.used_memory) };
+
+            let new_program = PioSpiProgram::new(pio, config.phase);
+
+            self.cfg.use_program(&new_program.prg, &[&self.clk_pin]);
+            self.program = Some(new_program);
+        }
+
+        self.sm.set_config(&self.cfg);
+        self.sm.restart();
+
+        self.sm.set_enable(true);
+    }
+}
+
+fn calculate_clock_divider(frequency_hz: u32) -> fixed::FixedU32<U8> {
+    // we multiply by 4 since each clock period is equal to 4 instructions
+
+    let sys_freq = clk_sys_freq().to_fixed::<fixed::FixedU64<U8>>();
+    let target_freq = (frequency_hz * 4).to_fixed::<fixed::FixedU64<U8>>();
+    (sys_freq / target_freq).to_fixed()
+}
+
+impl<'d, PIO: Instance, const SM: usize> Spi<'d, PIO, SM, Blocking> {
+    /// Create an SPI driver in blocking mode.
+    pub fn new_blocking(
+        pio: &mut Common<'d, PIO>,
+        sm: StateMachine<'d, PIO, SM>,
+        clk: Peri<'d, impl PioPin>,
+        mosi: Peri<'d, impl PioPin>,
+        miso: Peri<'d, impl PioPin>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(pio, sm, clk, mosi, miso, None, None, config)
+    }
+}
+
+impl<'d, PIO: Instance, const SM: usize> Spi<'d, PIO, SM, Async> {
+    /// Create an SPI driver in async mode supporting DMA operations.
+    #[allow(clippy::too_many_arguments)]
+    pub fn new(
+        pio: &mut Common<'d, PIO>,
+        sm: StateMachine<'d, PIO, SM>,
+        clk: Peri<'d, impl PioPin>,
+        mosi: Peri<'d, impl PioPin>,
+        miso: Peri<'d, impl PioPin>,
+        tx_dma: Peri<'d, impl Channel>,
+        rx_dma: Peri<'d, impl Channel>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            pio,
+            sm,
+            clk,
+            mosi,
+            miso,
+            Some(tx_dma.into()),
+            Some(rx_dma.into()),
+            config,
+        )
+    }
+
+    /// Read data from SPI using DMA.
+    pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
+        let (rx, tx) = self.sm.rx_tx();
+
+        let len = buffer.len();
+
+        let rx_ch = self.rx_dma.as_mut().unwrap().reborrow();
+        let rx_transfer = rx.dma_pull(rx_ch, buffer, false);
+
+        let tx_ch = self.tx_dma.as_mut().unwrap().reborrow();
+        let tx_transfer = tx.dma_push_repeated::<_, u8>(tx_ch, len);
+
+        join(tx_transfer, rx_transfer).await;
+
+        Ok(())
+    }
+
+    /// Write data to SPI using DMA.
+    pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
+        let (rx, tx) = self.sm.rx_tx();
+
+        let rx_ch = self.rx_dma.as_mut().unwrap().reborrow();
+        let rx_transfer = rx.dma_pull_repeated::<_, u8>(rx_ch, buffer.len());
+
+        let tx_ch = self.tx_dma.as_mut().unwrap().reborrow();
+        let tx_transfer = tx.dma_push(tx_ch, buffer, false);
+
+        join(tx_transfer, rx_transfer).await;
+
+        Ok(())
+    }
+
+    /// Transfer data to SPI using DMA.
+    pub async fn transfer(&mut self, rx_buffer: &mut [u8], tx_buffer: &[u8]) -> Result<(), Error> {
+        self.transfer_inner(rx_buffer, tx_buffer).await
+    }
+
+    /// Transfer data in place to SPI using DMA.
+    pub async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Error> {
+        self.transfer_inner(words, words).await
+    }
+
+    async fn transfer_inner(&mut self, rx_buffer: *mut [u8], tx_buffer: *const [u8]) -> Result<(), Error> {
+        let (rx, tx) = self.sm.rx_tx();
+
+        let mut rx_ch = self.rx_dma.as_mut().unwrap().reborrow();
+        let rx_transfer = async {
+            rx.dma_pull(rx_ch.reborrow(), unsafe { &mut *rx_buffer }, false).await;
+
+            if tx_buffer.len() > rx_buffer.len() {
+                let read_bytes_len = tx_buffer.len() - rx_buffer.len();
+
+                rx.dma_pull_repeated::<_, u8>(rx_ch, read_bytes_len).await;
+            }
+        };
+
+        let mut tx_ch = self.tx_dma.as_mut().unwrap().reborrow();
+        let tx_transfer = async {
+            tx.dma_push(tx_ch.reborrow(), unsafe { &*tx_buffer }, false).await;
+
+            if rx_buffer.len() > tx_buffer.len() {
+                let write_bytes_len = rx_buffer.len() - tx_buffer.len();
+
+                tx.dma_push_repeated::<_, u8>(tx_ch, write_bytes_len).await;
+            }
+        };
+
+        join(tx_transfer, rx_transfer).await;
+
+        Ok(())
+    }
+}
+
+// ====================
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> embedded_hal_02::blocking::spi::Transfer<u8> for Spi<'d, PIO, SM, M> {
+    type Error = Error;
+    fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
+        self.blocking_transfer_in_place(words)?;
+        Ok(words)
+    }
+}
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> embedded_hal_02::blocking::spi::Write<u8> for Spi<'d, PIO, SM, M> {
+    type Error = Error;
+
+    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_write(words)
+    }
+}
+
+impl embedded_hal_1::spi::Error for Error {
+    fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
+        match *self {}
+    }
+}
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> embedded_hal_1::spi::ErrorType for Spi<'d, PIO, SM, M> {
+    type Error = Error;
+}
+
+impl<'d, PIO: Instance, const SM: usize, M: Mode> embedded_hal_1::spi::SpiBus<u8> for Spi<'d, PIO, SM, M> {
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        Ok(())
+    }
+
+    fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.blocking_transfer(words, &[])
+    }
+
+    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_write(words)
+    }
+
+    fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
+        self.blocking_transfer(read, write)
+    }
+
+    fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.blocking_transfer_in_place(words)
+    }
+}
+
+impl<'d, PIO: Instance, const SM: usize> embedded_hal_async::spi::SpiBus<u8> for Spi<'d, PIO, SM, Async> {
+    async fn flush(&mut self) -> Result<(), Self::Error> {
+        Ok(())
+    }
+
+    async fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
+        self.write(words).await
+    }
+
+    async fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.read(words).await
+    }
+
+    async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
+        self.transfer(read, write).await
+    }
+
+    async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
+        self.transfer_in_place(words).await
+    }
+}
diff --git a/embassy-rp/src/pio_programs/ws2812.rs b/embassy-rp/src/pio_programs/ws2812.rs
index 578937e11..37dd1c4e0 100644
--- a/embassy-rp/src/pio_programs/ws2812.rs
+++ b/embassy-rp/src/pio_programs/ws2812.rs
@@ -2,7 +2,7 @@
 
 use embassy_time::Timer;
 use fixed::types::U24F8;
-use smart_leds::RGB8;
+use smart_leds::{RGB8, RGBW};
 
 use crate::clocks::clk_sys_freq;
 use crate::dma::{AnyChannel, Channel};
@@ -50,7 +50,7 @@ impl<'a, PIO: Instance> PioWs2812Program<'a, PIO> {
     }
 }
 
-/// Pio backed ws2812 driver
+/// Pio backed RGB ws2812 driver
 /// Const N is the number of ws2812 leds attached to this pin
 pub struct PioWs2812<'d, P: Instance, const S: usize, const N: usize> {
     dma: Peri<'d, AnyChannel>,
@@ -111,3 +111,69 @@ impl<'d, P: Instance, const S: usize, const N: usize> PioWs2812<'d, P, S, N> {
         Timer::after_micros(55).await;
     }
 }
+
+/// Pio backed RGBW ws2812 driver
+/// This version is intended for ws2812 leds with 4 addressable lights
+/// Const N is the number of ws2812 leds attached to this pin
+pub struct RgbwPioWs2812<'d, P: Instance, const S: usize, const N: usize> {
+    dma: Peri<'d, AnyChannel>,
+    sm: StateMachine<'d, P, S>,
+}
+
+impl<'d, P: Instance, const S: usize, const N: usize> RgbwPioWs2812<'d, P, S, N> {
+    /// Configure a pio state machine to use the loaded ws2812 program.
+    pub fn new(
+        pio: &mut Common<'d, P>,
+        mut sm: StateMachine<'d, P, S>,
+        dma: Peri<'d, impl Channel>,
+        pin: Peri<'d, impl PioPin>,
+        program: &PioWs2812Program<'d, P>,
+    ) -> Self {
+        // Setup sm0
+        let mut cfg = Config::default();
+
+        // Pin config
+        let out_pin = pio.make_pio_pin(pin);
+        cfg.set_out_pins(&[&out_pin]);
+        cfg.set_set_pins(&[&out_pin]);
+
+        cfg.use_program(&program.prg, &[&out_pin]);
+
+        // Clock config, measured in kHz to avoid overflows
+        let clock_freq = U24F8::from_num(clk_sys_freq() / 1000);
+        let ws2812_freq = U24F8::from_num(800);
+        let bit_freq = ws2812_freq * CYCLES_PER_BIT;
+        cfg.clock_divider = clock_freq / bit_freq;
+
+        // FIFO config
+        cfg.fifo_join = FifoJoin::TxOnly;
+        cfg.shift_out = ShiftConfig {
+            auto_fill: true,
+            threshold: 32,
+            direction: ShiftDirection::Left,
+        };
+
+        sm.set_config(&cfg);
+        sm.set_enable(true);
+
+        Self { dma: dma.into(), sm }
+    }
+
+    /// Write a buffer of [smart_leds::RGBW] to the ws2812 string
+    pub async fn write(&mut self, colors: &[RGBW<u8>; N]) {
+        // Precompute the word bytes from the colors
+        let mut words = [0u32; N];
+        for i in 0..N {
+            let word = (u32::from(colors[i].g) << 24)
+                | (u32::from(colors[i].r) << 16)
+                | (u32::from(colors[i].b) << 8)
+                | u32::from(colors[i].a.0);
+            words[i] = word;
+        }
+
+        // DMA transfer
+        self.sm.tx().dma_push(self.dma.reborrow(), &words, false).await;
+
+        Timer::after_micros(55).await;
+    }
+}