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authorMathias <[email protected]>2024-07-17 11:25:03 +0200
committerMathias <[email protected]>2024-07-17 11:25:03 +0200
commitf733071908ced05bc006b43e1383336290faafdc (patch)
tree3d930b0de2022fea2eff2f105b67a43f7b18ef3d /embassy-rp/src/uart/mod.rs
parente54c753537b4b12c3d2fd03ad8e8ba9eaaded06e (diff)
Add split_ref fn to uart, allowing a mutable reference split into RX & TX handles. Also change order of RX and TX handles in split fn, to streamline with other HALs
Diffstat (limited to 'embassy-rp/src/uart/mod.rs')
-rw-r--r--embassy-rp/src/uart/mod.rs28
1 files changed, 27 insertions, 1 deletions
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index 30ece15bd..f7c90e97b 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -7,7 +7,7 @@ use atomic_polyfill::{AtomicU16, Ordering};
7use embassy_futures::select::{select, Either}; 7use embassy_futures::select::{select, Either};
8use embassy_hal_internal::{into_ref, PeripheralRef}; 8use embassy_hal_internal::{into_ref, PeripheralRef};
9use embassy_sync::waitqueue::AtomicWaker; 9use embassy_sync::waitqueue::AtomicWaker;
10use embassy_time::Timer; 10use embassy_time::{Delay, Timer};
11use pac::uart::regs::Uartris; 11use pac::uart::regs::Uartris;
12 12
13use crate::clocks::clk_peri_freq; 13use crate::clocks::clk_peri_freq;
@@ -886,9 +886,28 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
886 r.uartibrd().write_value(pac::uart::regs::Uartibrd(baud_ibrd)); 886 r.uartibrd().write_value(pac::uart::regs::Uartibrd(baud_ibrd));
887 r.uartfbrd().write_value(pac::uart::regs::Uartfbrd(baud_fbrd)); 887 r.uartfbrd().write_value(pac::uart::regs::Uartfbrd(baud_fbrd));
888 888
889 let cr = r.uartcr().read();
890 if cr.uarten() {
891 r.uartcr().modify(|w| {
892 w.set_uarten(false);
893 w.set_txe(false);
894 w.set_rxe(false);
895 });
896
897 // Note: Maximise precision here. Show working, the compiler will mop this up.
898 // Create a 16.6 fixed-point fractional division ratio; then scale to 32-bits.
899 let mut brdiv_ratio = 64 * r.uartibrd().read().0 + r.uartfbrd().read().0;
900 brdiv_ratio <<= 10;
901 // 3662 is ~(15 * 244.14) where 244.14 is 16e6 / 2^16
902 let scaled_freq = clk_base / 3662;
903 let wait_time_us = brdiv_ratio / scaled_freq;
904 embedded_hal_1::delay::DelayNs::delay_us(&mut Delay, wait_time_us);
905 }
889 // PL011 needs a (dummy) line control register write to latch in the 906 // PL011 needs a (dummy) line control register write to latch in the
890 // divisors. We don't want to actually change LCR contents here. 907 // divisors. We don't want to actually change LCR contents here.
891 r.uartlcr_h().modify(|_| {}); 908 r.uartlcr_h().modify(|_| {});
909
910 r.uartcr().write_value(cr);
892 } 911 }
893} 912}
894 913
@@ -923,6 +942,13 @@ impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
923 pub fn split(self) -> (UartTx<'d, T, M>, UartRx<'d, T, M>) { 942 pub fn split(self) -> (UartTx<'d, T, M>, UartRx<'d, T, M>) {
924 (self.tx, self.rx) 943 (self.tx, self.rx)
925 } 944 }
945
946 /// Split the Uart into a transmitter and receiver by mutable reference,
947 /// which is particularly useful when having two tasks correlating to
948 /// transmitting and receiving.
949 pub fn split_ref(&mut self) -> (&mut UartTx<'d, T, M>, &mut UartRx<'d, T, M>) {
950 (&mut self.tx, &mut self.rx)
951 }
926} 952}
927 953
928impl<'d, T: Instance> Uart<'d, T, Async> { 954impl<'d, T: Instance> Uart<'d, T, Async> {