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authorCaleb Jamison <[email protected]>2024-08-07 23:20:26 -0400
committerCaleb Jamison <[email protected]>2024-08-08 21:35:21 -0400
commitb185e02a42ad751ec6c31ffa6a1b87503f15489d (patch)
tree0f0c66747267d24d95b5957b22db7e5c525cb00e /embassy-rp/src/uart
parent891c5ee10584cd990dad529e3506fe1328e4e69d (diff)
Initial rp235x support
Examples have been run, but there is not yet a test suite.
Diffstat (limited to 'embassy-rp/src/uart')
-rw-r--r--embassy-rp/src/uart/mod.rs122
1 files changed, 116 insertions, 6 deletions
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index d50f5b4d5..058cfcbee 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -247,7 +247,7 @@ impl<'d, T: Instance> UartTx<'d, T, Async> {
247 }); 247 });
248 // If we don't assign future to a variable, the data register pointer 248 // If we don't assign future to a variable, the data register pointer
249 // is held across an await and makes the future non-Send. 249 // is held across an await and makes the future non-Send.
250 crate::dma::write(ch, buffer, T::regs().uartdr().as_ptr() as *mut _, T::TX_DREQ) 250 crate::dma::write(ch, buffer, T::regs().uartdr().as_ptr() as *mut _, T::TX_DREQ.into())
251 }; 251 };
252 transfer.await; 252 transfer.await;
253 Ok(()) 253 Ok(())
@@ -422,7 +422,7 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
422 let transfer = unsafe { 422 let transfer = unsafe {
423 // If we don't assign future to a variable, the data register pointer 423 // If we don't assign future to a variable, the data register pointer
424 // is held across an await and makes the future non-Send. 424 // is held across an await and makes the future non-Send.
425 crate::dma::read(ch, T::regs().uartdr().as_ptr() as *const _, buffer, T::RX_DREQ) 425 crate::dma::read(ch, T::regs().uartdr().as_ptr() as *const _, buffer, T::RX_DREQ.into())
426 }; 426 };
427 427
428 // wait for either the transfer to complete or an error to happen. 428 // wait for either the transfer to complete or an error to happen.
@@ -571,7 +571,12 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
571 let transfer = unsafe { 571 let transfer = unsafe {
572 // If we don't assign future to a variable, the data register pointer 572 // If we don't assign future to a variable, the data register pointer
573 // is held across an await and makes the future non-Send. 573 // is held across an await and makes the future non-Send.
574 crate::dma::read(&mut ch, T::regs().uartdr().as_ptr() as *const _, sbuffer, T::RX_DREQ) 574 crate::dma::read(
575 &mut ch,
576 T::regs().uartdr().as_ptr() as *const _,
577 sbuffer,
578 T::RX_DREQ.into(),
579 )
575 }; 580 };
576 581
577 // wait for either the transfer to complete or an error to happen. 582 // wait for either the transfer to complete or an error to happen.
@@ -830,8 +835,16 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
830 ) { 835 ) {
831 let r = T::regs(); 836 let r = T::regs();
832 if let Some(pin) = &tx { 837 if let Some(pin) = &tx {
838 let funcsel = {
839 let pin_number = ((pin.gpio().as_ptr() as u32) & 0x1FF) / 8;
840 if (pin_number % 4) == 0 {
841 2
842 } else {
843 11
844 }
845 };
833 pin.gpio().ctrl().write(|w| { 846 pin.gpio().ctrl().write(|w| {
834 w.set_funcsel(2); 847 w.set_funcsel(funcsel);
835 w.set_outover(if config.invert_tx { 848 w.set_outover(if config.invert_tx {
836 Outover::INVERT 849 Outover::INVERT
837 } else { 850 } else {
@@ -841,8 +854,16 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
841 pin.pad_ctrl().write(|w| w.set_ie(true)); 854 pin.pad_ctrl().write(|w| w.set_ie(true));
842 } 855 }
843 if let Some(pin) = &rx { 856 if let Some(pin) = &rx {
857 let funcsel = {
858 let pin_number = ((pin.gpio().as_ptr() as u32) & 0x1FF) / 8;
859 if ((pin_number - 1) % 4) == 0 {
860 2
861 } else {
862 11
863 }
864 };
844 pin.gpio().ctrl().write(|w| { 865 pin.gpio().ctrl().write(|w| {
845 w.set_funcsel(2); 866 w.set_funcsel(funcsel);
846 w.set_inover(if config.invert_rx { 867 w.set_inover(if config.invert_rx {
847 Inover::INVERT 868 Inover::INVERT
848 } else { 869 } else {
@@ -904,7 +925,7 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
904 }); 925 });
905 } 926 }
906 927
907 fn lcr_modify<R>(f: impl FnOnce(&mut rp_pac::uart::regs::UartlcrH) -> R) -> R { 928 fn lcr_modify<R>(f: impl FnOnce(&mut crate::pac::uart::regs::UartlcrH) -> R) -> R {
908 let r = T::regs(); 929 let r = T::regs();
909 930
910 // Notes from PL011 reference manual: 931 // Notes from PL011 reference manual:
@@ -1332,3 +1353,92 @@ impl_pin!(PIN_26, UART1, CtsPin);
1332impl_pin!(PIN_27, UART1, RtsPin); 1353impl_pin!(PIN_27, UART1, RtsPin);
1333impl_pin!(PIN_28, UART0, TxPin); 1354impl_pin!(PIN_28, UART0, TxPin);
1334impl_pin!(PIN_29, UART0, RxPin); 1355impl_pin!(PIN_29, UART0, RxPin);
1356
1357// Additional functions added by all 2350s
1358#[cfg(feature = "rp235x")]
1359impl_pin!(PIN_2, UART0, TxPin);
1360#[cfg(feature = "rp235x")]
1361impl_pin!(PIN_3, UART0, RxPin);
1362#[cfg(feature = "rp235x")]
1363impl_pin!(PIN_6, UART1, TxPin);
1364#[cfg(feature = "rp235x")]
1365impl_pin!(PIN_7, UART1, RxPin);
1366#[cfg(feature = "rp235x")]
1367impl_pin!(PIN_10, UART1, TxPin);
1368#[cfg(feature = "rp235x")]
1369impl_pin!(PIN_11, UART1, RxPin);
1370#[cfg(feature = "rp235x")]
1371impl_pin!(PIN_14, UART0, TxPin);
1372#[cfg(feature = "rp235x")]
1373impl_pin!(PIN_15, UART0, RxPin);
1374#[cfg(feature = "rp235x")]
1375impl_pin!(PIN_18, UART0, TxPin);
1376#[cfg(feature = "rp235x")]
1377impl_pin!(PIN_19, UART0, RxPin);
1378#[cfg(feature = "rp235x")]
1379impl_pin!(PIN_22, UART1, TxPin);
1380#[cfg(feature = "rp235x")]
1381impl_pin!(PIN_23, UART1, RxPin);
1382#[cfg(feature = "rp235x")]
1383impl_pin!(PIN_26, UART1, TxPin);
1384#[cfg(feature = "rp235x")]
1385impl_pin!(PIN_27, UART1, RxPin);
1386
1387// Additional pins added by larger 2350 packages.
1388#[cfg(feature = "rp235xb")]
1389impl_pin!(PIN_30, UART0, CtsPin);
1390#[cfg(feature = "rp235xb")]
1391impl_pin!(PIN_31, UART0, RtsPin);
1392#[cfg(feature = "rp235xb")]
1393impl_pin!(PIN_32, UART0, TxPin);
1394#[cfg(feature = "rp235xb")]
1395impl_pin!(PIN_33, UART0, RxPin);
1396#[cfg(feature = "rp235xb")]
1397impl_pin!(PIN_34, UART0, CtsPin);
1398#[cfg(feature = "rp235xb")]
1399impl_pin!(PIN_35, UART0, RtsPin);
1400#[cfg(feature = "rp235xb")]
1401impl_pin!(PIN_36, UART1, TxPin);
1402#[cfg(feature = "rp235xb")]
1403impl_pin!(PIN_37, UART1, RxPin);
1404#[cfg(feature = "rp235xb")]
1405impl_pin!(PIN_38, UART1, CtsPin);
1406#[cfg(feature = "rp235xb")]
1407impl_pin!(PIN_39, UART1, RtsPin);
1408#[cfg(feature = "rp235xb")]
1409impl_pin!(PIN_40, UART1, TxPin);
1410#[cfg(feature = "rp235xb")]
1411impl_pin!(PIN_41, UART1, RxPin);
1412#[cfg(feature = "rp235xb")]
1413impl_pin!(PIN_42, UART1, CtsPin);
1414#[cfg(feature = "rp235xb")]
1415impl_pin!(PIN_43, UART1, RtsPin);
1416#[cfg(feature = "rp235xb")]
1417impl_pin!(PIN_44, UART0, TxPin);
1418#[cfg(feature = "rp235xb")]
1419impl_pin!(PIN_45, UART0, RxPin);
1420#[cfg(feature = "rp235xb")]
1421impl_pin!(PIN_46, UART0, CtsPin);
1422#[cfg(feature = "rp235xb")]
1423impl_pin!(PIN_47, UART0, RtsPin);
1424
1425#[cfg(feature = "rp235xb")]
1426impl_pin!(PIN_30, UART0, TxPin);
1427#[cfg(feature = "rp235xb")]
1428impl_pin!(PIN_31, UART0, RxPin);
1429#[cfg(feature = "rp235xb")]
1430impl_pin!(PIN_34, UART0, TxPin);
1431#[cfg(feature = "rp235xb")]
1432impl_pin!(PIN_35, UART0, RxPin);
1433#[cfg(feature = "rp235xb")]
1434impl_pin!(PIN_38, UART1, TxPin);
1435#[cfg(feature = "rp235xb")]
1436impl_pin!(PIN_39, UART1, RxPin);
1437#[cfg(feature = "rp235xb")]
1438impl_pin!(PIN_42, UART1, TxPin);
1439#[cfg(feature = "rp235xb")]
1440impl_pin!(PIN_43, UART1, RxPin);
1441#[cfg(feature = "rp235xb")]
1442impl_pin!(PIN_46, UART0, TxPin);
1443#[cfg(feature = "rp235xb")]
1444impl_pin!(PIN_47, UART0, RxPin);