diff options
| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2023-04-02 10:03:20 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-04-02 10:03:20 +0000 |
| commit | cd2ed065dc50e8540b17bfaecbf421679d2ab60d (patch) | |
| tree | c9282b2977cb6cb84755c405a0fab00e2f38ab23 /embassy-rp/src/uart | |
| parent | e3efda2249640e0b4881289aa609c96a26a7479a (diff) | |
| parent | 0e13fe992543980b1d05547bd2c7f7c08530a8d2 (diff) | |
Merge #1317
1317: Fix set_baudrate on RP-PICO r=Dirbaio a=TFleury
See [comment](https://github.com/embassy-rs/embassy/pull/1243#issuecomment-1492894626)
Co-authored-by: Thierry Fleury <[email protected]>
Diffstat (limited to 'embassy-rp/src/uart')
| -rw-r--r-- | embassy-rp/src/uart/mod.rs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs index 682243a27..a945f2295 100644 --- a/embassy-rp/src/uart/mod.rs +++ b/embassy-rp/src/uart/mod.rs | |||
| @@ -405,10 +405,6 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> { | |||
| 405 | Parity::ParityEven => (true, true), | 405 | Parity::ParityEven => (true, true), |
| 406 | }; | 406 | }; |
| 407 | 407 | ||
| 408 | // PL011 needs a (dummy) line control register write to latch in the | ||
| 409 | // divisors. We don't want to actually change LCR contents here. | ||
| 410 | r.uartlcr_h().modify(|_| {}); | ||
| 411 | |||
| 412 | r.uartlcr_h().write(|w| { | 408 | r.uartlcr_h().write(|w| { |
| 413 | w.set_wlen(config.data_bits.bits()); | 409 | w.set_wlen(config.data_bits.bits()); |
| 414 | w.set_stp2(config.stop_bits == StopBits::STOP2); | 410 | w.set_stp2(config.stop_bits == StopBits::STOP2); |
| @@ -458,6 +454,10 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> { | |||
| 458 | // Load PL011's baud divisor registers | 454 | // Load PL011's baud divisor registers |
| 459 | r.uartibrd().write_value(pac::uart::regs::Uartibrd(baud_ibrd)); | 455 | r.uartibrd().write_value(pac::uart::regs::Uartibrd(baud_ibrd)); |
| 460 | r.uartfbrd().write_value(pac::uart::regs::Uartfbrd(baud_fbrd)); | 456 | r.uartfbrd().write_value(pac::uart::regs::Uartfbrd(baud_fbrd)); |
| 457 | |||
| 458 | // PL011 needs a (dummy) line control register write to latch in the | ||
| 459 | // divisors. We don't want to actually change LCR contents here. | ||
| 460 | r.uartlcr_h().modify(|_| {}); | ||
| 461 | } | 461 | } |
| 462 | } | 462 | } |
| 463 | } | 463 | } |
