aboutsummaryrefslogtreecommitdiff
path: root/embassy-rp/src
diff options
context:
space:
mode:
authorHenrik Alsér <[email protected]>2022-08-31 21:54:42 +0200
committerHenrik Alsér <[email protected]>2022-09-01 15:12:44 +0200
commit3fce6ec649953fac52b731ea0aa7587ed60e55c9 (patch)
tree46fa14070d210a383b816baf184eced20bf8e1d4 /embassy-rp/src
parent27905f1be1e2404952b1a5c333d4a07f2e4c18f2 (diff)
Rearrange new:s
Diffstat (limited to 'embassy-rp/src')
-rw-r--r--embassy-rp/src/spi.rs176
-rw-r--r--embassy-rp/src/uart.rs16
2 files changed, 128 insertions, 64 deletions
diff --git a/embassy-rp/src/spi.rs b/embassy-rp/src/spi.rs
index 720aad0e5..9bf6a9119 100644
--- a/embassy-rp/src/spi.rs
+++ b/embassy-rp/src/spi.rs
@@ -65,66 +65,6 @@ fn calc_prescs(freq: u32) -> (u8, u8) {
65} 65}
66 66
67impl<'d, T: Instance, M: Mode> Spi<'d, T, M> { 67impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
68 pub fn new_blocking(
69 inner: impl Peripheral<P = T> + 'd,
70 clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
71 mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
72 miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
73 config: Config,
74 ) -> Self {
75 into_ref!(clk, mosi, miso);
76 Self::new_inner(
77 inner,
78 None,
79 None,
80 Some(clk.map_into()),
81 Some(mosi.map_into()),
82 Some(miso.map_into()),
83 None,
84 config,
85 )
86 }
87
88 pub fn new_txonly(
89 inner: impl Peripheral<P = T> + 'd,
90 tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
91 clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
92 mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
93 config: Config,
94 ) -> Self {
95 into_ref!(clk, mosi);
96 Self::new_inner(
97 inner,
98 tx_dma,
99 None,
100 Some(clk.map_into()),
101 Some(mosi.map_into()),
102 None,
103 None,
104 config,
105 )
106 }
107
108 pub fn new_rxonly(
109 inner: impl Peripheral<P = T> + 'd,
110 rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
111 clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
112 miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
113 config: Config,
114 ) -> Self {
115 into_ref!(clk, miso);
116 Self::new_inner(
117 inner,
118 None,
119 rx_dma,
120 Some(clk.map_into()),
121 None,
122 Some(miso.map_into()),
123 None,
124 config,
125 )
126 }
127
128 fn new_inner( 68 fn new_inner(
129 inner: impl Peripheral<P = T> + 'd, 69 inner: impl Peripheral<P = T> + 'd,
130 tx_dma: Option<PeripheralRef<'d, AnyChannel>>, 70 tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
@@ -261,6 +201,66 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
261 } 201 }
262} 202}
263 203
204impl<'d, T: Instance> Spi<'d, T, Blocking> {
205 pub fn new_blocking(
206 inner: impl Peripheral<P = T> + 'd,
207 clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
208 mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
209 miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
210 config: Config,
211 ) -> Self {
212 into_ref!(clk, mosi, miso);
213 Self::new_inner(
214 inner,
215 None,
216 None,
217 Some(clk.map_into()),
218 Some(mosi.map_into()),
219 Some(miso.map_into()),
220 None,
221 config,
222 )
223 }
224
225 pub fn new_blocking_txonly(
226 inner: impl Peripheral<P = T> + 'd,
227 clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
228 mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
229 config: Config,
230 ) -> Self {
231 into_ref!(clk, mosi);
232 Self::new_inner(
233 inner,
234 None,
235 None,
236 Some(clk.map_into()),
237 Some(mosi.map_into()),
238 None,
239 None,
240 config,
241 )
242 }
243
244 pub fn new_blocking_rxonly(
245 inner: impl Peripheral<P = T> + 'd,
246 clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
247 miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
248 config: Config,
249 ) -> Self {
250 into_ref!(clk, miso);
251 Self::new_inner(
252 inner,
253 None,
254 None,
255 Some(clk.map_into()),
256 None,
257 Some(miso.map_into()),
258 None,
259 config,
260 )
261 }
262}
263
264impl<'d, T: Instance> Spi<'d, T, Async> { 264impl<'d, T: Instance> Spi<'d, T, Async> {
265 pub fn new( 265 pub fn new(
266 inner: impl Peripheral<P = T> + 'd, 266 inner: impl Peripheral<P = T> + 'd,
@@ -284,6 +284,46 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
284 ) 284 )
285 } 285 }
286 286
287 pub fn new_txonly(
288 inner: impl Peripheral<P = T> + 'd,
289 tx_dma: impl Peripheral<P = impl Channel> + 'd,
290 clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
291 mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
292 config: Config,
293 ) -> Self {
294 into_ref!(tx_dma, clk, mosi);
295 Self::new_inner(
296 inner,
297 Some(tx_dma.map_into()),
298 None,
299 Some(clk.map_into()),
300 Some(mosi.map_into()),
301 None,
302 None,
303 config,
304 )
305 }
306
307 pub fn new_rxonly(
308 inner: impl Peripheral<P = T> + 'd,
309 rx_dma: impl Peripheral<P = impl Channel> + 'd,
310 clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
311 miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
312 config: Config,
313 ) -> Self {
314 into_ref!(rx_dma, clk, miso);
315 Self::new_inner(
316 inner,
317 None,
318 Some(rx_dma.map_into()),
319 Some(clk.map_into()),
320 None,
321 Some(miso.map_into()),
322 None,
323 config,
324 )
325 }
326
287 pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> { 327 pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
288 let (from_ptr, len) = crate::dma::slice_ptr_parts(buffer); 328 let (from_ptr, len) = crate::dma::slice_ptr_parts(buffer);
289 let ch = self.tx_dma.as_mut().unwrap(); 329 let ch = self.tx_dma.as_mut().unwrap();
@@ -293,7 +333,13 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
293 }); 333 });
294 // If we don't assign future to a variable, the data register pointer 334 // If we don't assign future to a variable, the data register pointer
295 // is held across an await and makes the future non-Send. 335 // is held across an await and makes the future non-Send.
296 crate::dma::write(ch, from_ptr as *const u32, self.inner.regs().dr().ptr() as *mut _, len, T::TX_DREQ) 336 crate::dma::write(
337 ch,
338 from_ptr as *const u32,
339 self.inner.regs().dr().ptr() as *mut _,
340 len,
341 T::TX_DREQ,
342 )
297 }; 343 };
298 transfer.await; 344 transfer.await;
299 Ok(()) 345 Ok(())
@@ -308,7 +354,13 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
308 }); 354 });
309 // If we don't assign future to a variable, the data register pointer 355 // If we don't assign future to a variable, the data register pointer
310 // is held across an await and makes the future non-Send. 356 // is held across an await and makes the future non-Send.
311 crate::dma::read(ch, self.inner.regs().dr().ptr() as *const _, to_ptr as *mut u32, len, T::RX_DREQ) 357 crate::dma::read(
358 ch,
359 self.inner.regs().dr().ptr() as *const _,
360 to_ptr as *mut u32,
361 len,
362 T::RX_DREQ,
363 )
312 }; 364 };
313 transfer.await; 365 transfer.await;
314 Ok(()) 366 Ok(())
diff --git a/embassy-rp/src/uart.rs b/embassy-rp/src/uart.rs
index f8a10bd9d..87d5fbd46 100644
--- a/embassy-rp/src/uart.rs
+++ b/embassy-rp/src/uart.rs
@@ -128,7 +128,13 @@ impl<'d, T: Instance> UartTx<'d, T, Async> {
128 }); 128 });
129 // If we don't assign future to a variable, the data register pointer 129 // If we don't assign future to a variable, the data register pointer
130 // is held across an await and makes the future non-Send. 130 // is held across an await and makes the future non-Send.
131 crate::dma::write(ch, from_ptr as *const u32, T::regs().uartdr().ptr() as *mut _, len, T::TX_DREQ) 131 crate::dma::write(
132 ch,
133 from_ptr as *const u32,
134 T::regs().uartdr().ptr() as *mut _,
135 len,
136 T::TX_DREQ,
137 )
132 }; 138 };
133 transfer.await; 139 transfer.await;
134 Ok(()) 140 Ok(())
@@ -182,7 +188,13 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
182 }); 188 });
183 // If we don't assign future to a variable, the data register pointer 189 // If we don't assign future to a variable, the data register pointer
184 // is held across an await and makes the future non-Send. 190 // is held across an await and makes the future non-Send.
185 crate::dma::read(ch, T::regs().uartdr().ptr() as *const _, to_ptr as *mut u32, len, T::RX_DREQ) 191 crate::dma::read(
192 ch,
193 T::regs().uartdr().ptr() as *const _,
194 to_ptr as *mut u32,
195 len,
196 T::RX_DREQ,
197 )
186 }; 198 };
187 transfer.await; 199 transfer.await;
188 Ok(()) 200 Ok(())
generated by cgit (git 2.34.1) at 2026-04-05 22:26:11 +0000