rp/pio: only clear diag bits if they're set

otherwise we may lose a bit being raised after it was read, but before
it was cleared.

1 files changed, 12 insertions, 4 deletions

diff --git a/embassy-rp/src/pio.rs b/embassy-rp/src/pio.rs
index d2eedc72a..ea6814fb8 100644
--- a/embassy-rp/src/pio.rs
+++ b/embassy-rp/src/pio.rs
@@ -307,7 +307,9 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineRx<'d, PIO, SM> {
         unsafe {
             let fdebug = PIO::PIO.fdebug();
             let ret = fdebug.read().rxstall() & (1 << SM) != 0;
-            fdebug.write(|w| w.set_rxstall(1 << SM));
+            if ret {
+                fdebug.write(|w| w.set_rxstall(1 << SM));
+            }
             ret
         }
     }
@@ -316,7 +318,9 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineRx<'d, PIO, SM> {
         unsafe {
             let fdebug = PIO::PIO.fdebug();
             let ret = fdebug.read().rxunder() & (1 << SM) != 0;
-            fdebug.write(|w| w.set_rxunder(1 << SM));
+            if ret {
+                fdebug.write(|w| w.set_rxunder(1 << SM));
+            }
             ret
         }
     }
@@ -383,7 +387,9 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM> {
         unsafe {
             let fdebug = PIO::PIO.fdebug();
             let ret = fdebug.read().txstall() & (1 << SM) != 0;
-            fdebug.write(|w| w.set_txstall(1 << SM));
+            if ret {
+                fdebug.write(|w| w.set_txstall(1 << SM));
+            }
             ret
         }
     }
@@ -392,7 +398,9 @@ impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM> {
         unsafe {
             let fdebug = PIO::PIO.fdebug();
             let ret = fdebug.read().txover() & (1 << SM) != 0;
-            fdebug.write(|w| w.set_txover(1 << SM));
+            if ret {
+                fdebug.write(|w| w.set_txover(1 << SM));
+            }
             ret
         }
     }