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author9names <[email protected]>2025-09-21 13:24:29 +1000
committer9names <[email protected]>2025-09-21 19:12:31 +1000
commit9bb77f36f9697dd301f6c68a649030e2b5487782 (patch)
tree7078809aef156b76fc4ff7ab24cabc2f4889a18f /embassy-rp
parent8394e1320844f6a1342f1bff10215cfd4643fe3a (diff)
rp: Use msplim for rp235x core1 stack guard
Diffstat (limited to 'embassy-rp')
-rw-r--r--embassy-rp/src/lib.rs14
1 files changed, 3 insertions, 11 deletions
diff --git a/embassy-rp/src/lib.rs b/embassy-rp/src/lib.rs
index 6fb680b34..d03ba1fef 100644
--- a/embassy-rp/src/lib.rs
+++ b/embassy-rp/src/lib.rs
@@ -565,18 +565,10 @@ unsafe fn install_stack_guard(stack_bottom: *mut usize) -> Result<(), ()> {
565#[cfg(all(feature = "_rp235x", not(feature = "_test")))] 565#[cfg(all(feature = "_rp235x", not(feature = "_test")))]
566#[inline(always)] 566#[inline(always)]
567unsafe fn install_stack_guard(stack_bottom: *mut usize) -> Result<(), ()> { 567unsafe fn install_stack_guard(stack_bottom: *mut usize) -> Result<(), ()> {
568 let core = unsafe { cortex_m::Peripherals::steal() }; 568 // The RP2350 arm cores are cortex-m33 and can use the MSPLIM register to guard the end of stack.
569 // We'll need to do something else for the riscv cores.
570 cortex_m::register::msplim::write(stack_bottom.addr() as u32);
569 571
570 // Fail if MPU is already configured
571 if core.MPU.ctrl.read() != 0 {
572 return Err(());
573 }
574
575 unsafe {
576 core.MPU.ctrl.write(5); // enable mpu with background default map
577 core.MPU.rbar.write(stack_bottom as u32 & !0xff); // set address
578 core.MPU.rlar.write(((stack_bottom as usize + 255) as u32) | 1);
579 }
580 Ok(()) 572 Ok(())
581} 573}
582 574