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authorxoviat <[email protected]>2023-06-18 18:56:53 -0500
committerxoviat <[email protected]>2023-06-18 18:56:53 -0500
commit72fd648d92738546b03166922defd4bee2d5fa9d (patch)
tree4a304d14ac4e324cfe417aac7a98ca57483f7ceb /embassy-stm32-wpan
parentb95c0210b83d0742fa4663b2726e4e7b82a4e068 (diff)
stm32/wpan: add shci mac init
Diffstat (limited to 'embassy-stm32-wpan')
-rw-r--r--embassy-stm32-wpan/src/sys.rs6
1 files changed, 6 insertions, 0 deletions
diff --git a/embassy-stm32-wpan/src/sys.rs b/embassy-stm32-wpan/src/sys.rs
index 5fe09a20f..65a64e090 100644
--- a/embassy-stm32-wpan/src/sys.rs
+++ b/embassy-stm32-wpan/src/sys.rs
@@ -61,6 +61,12 @@ impl Sys {
61 } 61 }
62 } 62 }
63 63
64 #[cfg(feature = "mac")]
65 pub async fn shci_c2_mac_802_15_4_init(&self) -> SchiCommandStatus {
66 self.write_and_get_response(ShciOpcode::Mac802_15_4Init, &[]).await
67 }
68
69 #[cfg(feature = "ble")]
64 pub async fn shci_c2_ble_init(&self, param: ShciBleInitCmdParam) -> SchiCommandStatus { 70 pub async fn shci_c2_ble_init(&self, param: ShciBleInitCmdParam) -> SchiCommandStatus {
65 self.write_and_get_response(ShciOpcode::BleInit, param.payload()).await 71 self.write_and_get_response(ShciOpcode::BleInit, param.payload()).await
66 } 72 }