diff options
| author | WillaWillNot <[email protected]> | 2025-11-22 18:18:04 -0500 |
|---|---|---|
| committer | WillaWillNot <[email protected]> | 2025-11-22 18:18:04 -0500 |
| commit | b877b0dc6b5fe4541a45e6b43ed9d82131608aee (patch) | |
| tree | 6bc432aa7081bf6d2df36e322d5c742eaa449977 /embassy-stm32/build.rs | |
| parent | 2589d3539903356c524b38f04f740b1735a80207 (diff) | |
Build script now injects EXTI2 => EXTI2_TSC peripheral/interrupt mapping if it's not present in the PAC, removed macro magic in exti that was working around this omission
Diffstat (limited to 'embassy-stm32/build.rs')
| -rw-r--r-- | embassy-stm32/build.rs | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index 3d0b13fe2..109571e8f 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs | |||
| @@ -56,16 +56,12 @@ fn main() { | |||
| 56 | 56 | ||
| 57 | eprintln!("chip: {chip_name}"); | 57 | eprintln!("chip: {chip_name}"); |
| 58 | 58 | ||
| 59 | cfgs.declare("unimpl_tsc"); | ||
| 60 | for p in METADATA.peripherals { | 59 | for p in METADATA.peripherals { |
| 61 | if let Some(r) = &p.registers { | 60 | if let Some(r) = &p.registers { |
| 62 | cfgs.enable(r.kind); | 61 | cfgs.enable(r.kind); |
| 63 | foreach_version_cfg(&mut cfgs, r.kind, r.version, |cfgs, cfg_name| { | 62 | foreach_version_cfg(&mut cfgs, r.kind, r.version, |cfgs, cfg_name| { |
| 64 | cfgs.enable(cfg_name); | 63 | cfgs.enable(cfg_name); |
| 65 | }); | 64 | }); |
| 66 | } else if p.name == "TSC" { | ||
| 67 | //Even if the registers are missing, EXTI needs to know if TSC is present in silicon to know whether the EXTI2 interrupt is shadowed by EXTI2_TSC | ||
| 68 | cfgs.enable("unimpl_tsc") | ||
| 69 | } | 65 | } |
| 70 | } | 66 | } |
| 71 | 67 | ||
| @@ -357,8 +353,13 @@ fn main() { | |||
| 357 | // ======== | 353 | // ======== |
| 358 | // Generate interrupt declarations | 354 | // Generate interrupt declarations |
| 359 | 355 | ||
| 356 | let mut exti2_tsc_shared_int_present: Option<stm32_metapac::metadata::Interrupt> = None; | ||
| 360 | let mut irqs = Vec::new(); | 357 | let mut irqs = Vec::new(); |
| 361 | for irq in METADATA.interrupts { | 358 | for irq in METADATA.interrupts { |
| 359 | // The PAC doesn't ensure this is listed as the IRQ of EXTI2, so we must do so | ||
| 360 | if irq.name == "EXTI2_TSC" { | ||
| 361 | exti2_tsc_shared_int_present = Some(irq.clone()) | ||
| 362 | } | ||
| 362 | irqs.push(format_ident!("{}", irq.name)); | 363 | irqs.push(format_ident!("{}", irq.name)); |
| 363 | } | 364 | } |
| 364 | 365 | ||
| @@ -1816,7 +1817,19 @@ fn main() { | |||
| 1816 | for p in METADATA.peripherals { | 1817 | for p in METADATA.peripherals { |
| 1817 | let mut pt = TokenStream::new(); | 1818 | let mut pt = TokenStream::new(); |
| 1818 | 1819 | ||
| 1820 | let mut exti2_tsc_injected = false; | ||
| 1821 | if let Some(ref irq) = exti2_tsc_shared_int_present | ||
| 1822 | && p.name == "EXTI" | ||
| 1823 | { | ||
| 1824 | exti2_tsc_injected = true; | ||
| 1825 | let iname = format_ident!("{}", irq.name); | ||
| 1826 | let sname = format_ident!("{}", "EXTI2"); | ||
| 1827 | pt.extend(quote!(pub type #sname = crate::interrupt::typelevel::#iname;)); | ||
| 1828 | } | ||
| 1819 | for irq in p.interrupts { | 1829 | for irq in p.interrupts { |
| 1830 | if exti2_tsc_injected && irq.signal == "EXTI2" { | ||
| 1831 | continue; | ||
| 1832 | } | ||
| 1820 | let iname = format_ident!("{}", irq.interrupt); | 1833 | let iname = format_ident!("{}", irq.interrupt); |
| 1821 | let sname = format_ident!("{}", irq.signal); | 1834 | let sname = format_ident!("{}", irq.signal); |
| 1822 | pt.extend(quote!(pub type #sname = crate::interrupt::typelevel::#iname;)); | 1835 | pt.extend(quote!(pub type #sname = crate::interrupt::typelevel::#iname;)); |
