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authoreverdrone <[email protected]>2025-11-11 15:48:56 +0100
committereverdrone <[email protected]>2025-11-11 15:48:56 +0100
commitcede7216861a82b0db55f5a88afb3acf2ace6c4b (patch)
treed92fb578897c77f51317318c5b180931b7b25c63 /embassy-stm32/build.rs
parentcf55b39f9a54cf3ed01f52c0565a36a444174235 (diff)
parent3d1f09597335d3681699ba09a77da4b39ed984fd (diff)
Merge branch main into n6
Diffstat (limited to 'embassy-stm32/build.rs')
-rw-r--r--embassy-stm32/build.rs33
1 files changed, 30 insertions, 3 deletions
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 861f3fcee..09a05ce68 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -9,8 +9,8 @@ use proc_macro2::{Ident, TokenStream};
9use quote::{format_ident, quote}; 9use quote::{format_ident, quote};
10use stm32_metapac::metadata::ir::BitOffset; 10use stm32_metapac::metadata::ir::BitOffset;
11use stm32_metapac::metadata::{ 11use stm32_metapac::metadata::{
12 MemoryRegion, MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, StopMode, 12 ALL_CHIPS, ALL_PERIPHERAL_VERSIONS, METADATA, MemoryRegion, MemoryRegionKind, PeripheralRccKernelClock,
13 ALL_CHIPS, ALL_PERIPHERAL_VERSIONS, METADATA, 13 PeripheralRccRegister, PeripheralRegisters, StopMode,
14}; 14};
15 15
16#[path = "./build_common.rs"] 16#[path = "./build_common.rs"]
@@ -105,13 +105,17 @@ fn main() {
105 } 105 }
106 (false, false) => { 106 (false, false) => {
107 if METADATA.memory.len() != 1 { 107 if METADATA.memory.len() != 1 {
108 panic!("Chip supports single and dual bank configuration. No Cargo feature to select one is enabled. Use the 'single-bank' or 'dual-bank' feature to make your selection") 108 panic!(
109 "Chip supports single and dual bank configuration. No Cargo feature to select one is enabled. Use the 'single-bank' or 'dual-bank' feature to make your selection"
110 )
109 } 111 }
110 METADATA.memory[0] 112 METADATA.memory[0]
111 } 113 }
112 } 114 }
113 }; 115 };
114 116
117 let has_bkpsram = memory.iter().any(|m| m.name == "BKPSRAM");
118
115 // ======== 119 // ========
116 // Generate singletons 120 // Generate singletons
117 121
@@ -122,6 +126,13 @@ fn main() {
122 singletons.push(p.name.to_string()); 126 singletons.push(p.name.to_string());
123 } 127 }
124 128
129 cfgs.declare("backup_sram");
130
131 if has_bkpsram {
132 singletons.push("BKPSRAM".to_string());
133 cfgs.enable("backup_sram")
134 }
135
125 // generate one singleton per peripheral (with many exceptions...) 136 // generate one singleton per peripheral (with many exceptions...)
126 for p in METADATA.peripherals { 137 for p in METADATA.peripherals {
127 if let Some(r) = &p.registers { 138 if let Some(r) = &p.registers {
@@ -1995,6 +2006,18 @@ fn main() {
1995 )); 2006 ));
1996 2007
1997 // ======== 2008 // ========
2009 // Generate backup sram constants
2010 if let Some(m) = memory.iter().find(|m| m.name == "BKPSRAM") {
2011 let bkpsram_base = m.address as usize;
2012 let bkpsram_size = m.size as usize;
2013
2014 g.extend(quote!(
2015 pub const BKPSRAM_BASE: usize = #bkpsram_base;
2016 pub const BKPSRAM_SIZE: usize = #bkpsram_size;
2017 ));
2018 }
2019
2020 // ========
1998 // Generate flash constants 2021 // Generate flash constants
1999 2022
2000 if has_flash { 2023 if has_flash {
@@ -2323,6 +2346,10 @@ fn mem_filter(chip: &str, region: &str) -> bool {
2323 return false; 2346 return false;
2324 } 2347 }
2325 2348
2349 if region.starts_with("SDRAM_") || region.starts_with("FMC_") || region.starts_with("OCTOSPI_") {
2350 return false;
2351 }
2352
2326 true 2353 true
2327} 2354}
2328 2355