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authorxoviat <[email protected]>2023-09-27 20:58:46 -0500
committerxoviat <[email protected]>2023-09-27 20:58:46 -0500
commit79146c4bd5cdbd8337d0dbdfd93219b9cb330c47 (patch)
treee10d53df45b95db09e1d74d19a3abd269b736f69 /embassy-stm32/src/adc/v1.rs
parent20ea76c19c709abf652b9a044292eb26fd656223 (diff)
stm32/adc: cleanup f1, f3, v1, and v2
Diffstat (limited to 'embassy-stm32/src/adc/v1.rs')
-rw-r--r--embassy-stm32/src/adc/v1.rs35
1 files changed, 12 insertions, 23 deletions
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 15b2dc593..fded26e40 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -5,7 +5,7 @@ use core::task::Poll;
5use embassy_hal_internal::into_ref; 5use embassy_hal_internal::into_ref;
6use embedded_hal_02::blocking::delay::DelayUs; 6use embedded_hal_02::blocking::delay::DelayUs;
7 7
8use crate::adc::{Adc, AdcPin, Instance, InternalChannel, Resolution, SampleTime}; 8use crate::adc::{Adc, AdcPin, Instance, Resolution, SampleTime};
9use crate::interrupt::typelevel::Interrupt; 9use crate::interrupt::typelevel::Interrupt;
10use crate::peripherals::ADC; 10use crate::peripherals::ADC;
11use crate::{interrupt, Peripheral}; 11use crate::{interrupt, Peripheral};
@@ -31,24 +31,24 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
31} 31}
32 32
33pub struct Vbat; 33pub struct Vbat;
34impl InternalChannel<ADC> for Vbat {} 34impl AdcPin<ADC> for Vbat {}
35impl super::sealed::InternalChannel<ADC> for Vbat { 35impl super::sealed::AdcPin<ADC> for Vbat {
36 fn channel(&self) -> u8 { 36 fn channel(&self) -> u8 {
37 18 37 18
38 } 38 }
39} 39}
40 40
41pub struct Vref; 41pub struct Vref;
42impl InternalChannel<ADC> for Vref {} 42impl AdcPin<ADC> for Vref {}
43impl super::sealed::InternalChannel<ADC> for Vref { 43impl super::sealed::AdcPin<ADC> for Vref {
44 fn channel(&self) -> u8 { 44 fn channel(&self) -> u8 {
45 17 45 17
46 } 46 }
47} 47}
48 48
49pub struct Temperature; 49pub struct Temperature;
50impl InternalChannel<ADC> for Temperature {} 50impl AdcPin<ADC> for Temperature {}
51impl super::sealed::InternalChannel<ADC> for Temperature { 51impl super::sealed::AdcPin<ADC> for Temperature {
52 fn channel(&self) -> u8 { 52 fn channel(&self) -> u8 {
53 16 53 16
54 } 54 }
@@ -134,18 +134,14 @@ impl<'d, T: Instance> Adc<'d, T> {
134 T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into())); 134 T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
135 } 135 }
136 136
137 pub async fn read<P>(&mut self, pin: &mut P) -> u16 137 pub async fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 {
138 where
139 P: AdcPin<T> + crate::gpio::sealed::Pin,
140 {
141 let channel = pin.channel(); 138 let channel = pin.channel();
142 pin.set_as_analog(); 139 pin.set_as_analog();
143 self.read_channel(channel).await
144 }
145 140
146 pub async fn read_internal(&mut self, channel: &mut impl InternalChannel<T>) -> u16 { 141 // A.7.5 Single conversion sequence code example - Software trigger
147 let channel = channel.channel(); 142 T::regs().chselr().write(|reg| reg.set_chselx(channel as usize, true));
148 self.read_channel(channel).await 143
144 self.convert().await
149 } 145 }
150 146
151 async fn convert(&mut self) -> u16 { 147 async fn convert(&mut self) -> u16 {
@@ -171,13 +167,6 @@ impl<'d, T: Instance> Adc<'d, T> {
171 167
172 T::regs().dr().read().data() 168 T::regs().dr().read().data()
173 } 169 }
174
175 async fn read_channel(&mut self, channel: u8) -> u16 {
176 // A.7.5 Single conversion sequence code example - Software trigger
177 T::regs().chselr().write(|reg| reg.set_chselx(channel as usize, true));
178
179 self.convert().await
180 }
181} 170}
182 171
183impl<'d, T: Instance> Drop for Adc<'d, T> { 172impl<'d, T: Instance> Drop for Adc<'d, T> {