adc: type-erase regs instance

1 files changed, 44 insertions, 47 deletions

diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index b270588c4..9cc44aa9a 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -146,63 +146,63 @@ pub struct AdcConfig {
     pub averaging: Option<Averaging>,
 }
 
-impl<T: Instance> super::SealedAnyInstance for T {
-    fn dr() -> *mut u16 {
-        T::regs().dr().as_ptr() as *mut u16
+impl super::AdcRegs for crate::pac::adc::Adc {
+    fn data(&self) -> *mut u16 {
+        crate::pac::adc::Adc::dr(*self).as_ptr() as *mut u16
     }
 
     // Enable ADC only when it is not already running.
-    fn enable() {
+    fn enable(&self) {
         // Make sure bits are off
-        while T::regs().cr().read().addis() {
+        while self.cr().read().addis() {
             // spin
         }
 
-        if !T::regs().cr().read().aden() {
+        if !self.cr().read().aden() {
             // Enable ADC
-            T::regs().isr().modify(|reg| {
+            self.isr().modify(|reg| {
                 reg.set_adrdy(true);
             });
-            T::regs().cr().modify(|reg| {
+            self.cr().modify(|reg| {
                 reg.set_aden(true);
             });
 
-            while !T::regs().isr().read().adrdy() {
+            while !self.isr().read().adrdy() {
                 // spin
             }
         }
     }
 
-    fn start() {
-        T::regs().cr().modify(|reg| {
+    fn start(&self) {
+        self.cr().modify(|reg| {
             reg.set_adstart(true);
         });
     }
 
-    fn stop() {
+    fn stop(&self) {
         // Ensure conversions are finished.
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
+        if self.cr().read().adstart() && !self.cr().read().addis() {
+            self.cr().modify(|reg| {
                 reg.set_adstp(true);
             });
-            while T::regs().cr().read().adstart() {}
+            while self.cr().read().adstart() {}
         }
 
         // Reset configuration.
         #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
+        self.cfgr().modify(|reg| {
             reg.set_cont(false);
             reg.set_dmaen(false);
         });
         #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
+        self.cfgr1().modify(|reg| {
             reg.set_cont(false);
             reg.set_dmaen(false);
         });
     }
 
     /// Perform a single conversion.
-    fn convert() -> u16 {
+    fn convert(&self) {
         // Some models are affected by an erratum:
         // If we perform conversions slower than 1 kHz, the first read ADC value can be
         // corrupted, so we discard it and measure again.
@@ -216,36 +216,34 @@ impl<T: Instance> super::SealedAnyInstance for T {
         let len = 1;
 
         for _ in 0..len {
-            T::regs().isr().modify(|reg| {
+            self.isr().modify(|reg| {
                 reg.set_eos(true);
                 reg.set_eoc(true);
             });
 
             // Start conversion
-            T::regs().cr().modify(|reg| {
+            self.cr().modify(|reg| {
                 reg.set_adstart(true);
             });
 
-            while !T::regs().isr().read().eos() {
+            while !self.isr().read().eos() {
                 // spin
             }
         }
-
-        T::regs().dr().read().0 as u16
     }
 
-    fn configure_dma(conversion_mode: ConversionMode) {
+    fn configure_dma(&self, conversion_mode: ConversionMode) {
         // Set continuous mode with oneshot dma.
         // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
+        self.isr().modify(|reg| {
             reg.set_ovr(true);
         });
 
         #[cfg(not(any(adc_g0, adc_u0)))]
-        let regs = T::regs().cfgr();
+        let regs = self.cfgr();
 
         #[cfg(any(adc_g0, adc_u0))]
-        let regs = T::regs().cfgr1();
+        let regs = self.cfgr1();
 
         regs.modify(|reg| {
             reg.set_discen(false);
@@ -259,13 +257,13 @@ impl<T: Instance> super::SealedAnyInstance for T {
         });
     }
 
-    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+    fn configure_sequence(&self, sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
         #[cfg(adc_h5)]
-        T::regs().cr().modify(|w| w.set_aden(false));
+        self.cr().modify(|w| w.set_aden(false));
 
         // Set sequence length
         #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().sqr1().modify(|w| {
+        self.sqr1().modify(|w| {
             w.set_l(sequence.len() as u8 - 1);
         });
 
@@ -273,8 +271,8 @@ impl<T: Instance> super::SealedAnyInstance for T {
         {
             let mut sample_times = Vec::<SampleTime, SAMPLE_TIMES_CAPACITY>::new();
 
-            T::regs().chselr().write(|chselr| {
-                T::regs().smpr().write(|smpr| {
+            self.chselr().write(|chselr| {
+                self.smpr().write(|smpr| {
                     for ((channel, _), sample_time) in sequence {
                         chselr.set_chsel(channel.into(), true);
                         if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
@@ -306,22 +304,22 @@ impl<T: Instance> super::SealedAnyInstance for T {
                 // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
                 #[cfg(any(adc_h5, adc_h7rs))]
                 if channel == 0 {
-                    T::regs().or().modify(|reg| reg.set_op0(true));
+                    self.or().modify(|reg| reg.set_op0(true));
                 }
 
                 // Configure channel
                 cfg_if! {
                     if #[cfg(adc_u0)] {
                         // On G0 and U6 all channels use the same sampling time.
-                        T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+                        self.smpr().modify(|reg| reg.set_smp1(sample_time.into()));
                     } else if #[cfg(any(adc_h5, adc_h7rs))] {
                         match channel {
-                            0..=9 => T::regs().smpr1().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
-                            _ => T::regs().smpr2().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                            0..=9 => self.smpr1().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                            _ => self.smpr2().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
                         }
                     } else {
                         let sample_time = sample_time.into();
-                        T::regs()
+                        self
                             .smpr(channel as usize / 10)
                             .modify(|reg| reg.set_smp(channel as usize % 10, sample_time));
                     }
@@ -331,9 +329,8 @@ impl<T: Instance> super::SealedAnyInstance for T {
                 {
                     use crate::pac::adc::vals::Pcsel;
 
-                    T::regs().cfgr2().modify(|w| w.set_lshift(0));
-                    T::regs()
-                        .pcsel()
+                    self.cfgr2().modify(|w| w.set_lshift(0));
+                    self.pcsel()
                         .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
                 }
 
@@ -341,22 +338,22 @@ impl<T: Instance> super::SealedAnyInstance for T {
                 #[cfg(not(any(adc_g0, adc_u0)))]
                 match _i {
                     0..=3 => {
-                        T::regs().sqr1().modify(|w| {
+                        self.sqr1().modify(|w| {
                             w.set_sq(_i, channel);
                         });
                     }
                     4..=8 => {
-                        T::regs().sqr2().modify(|w| {
+                        self.sqr2().modify(|w| {
                             w.set_sq(_i - 4, channel);
                         });
                     }
                     9..=13 => {
-                        T::regs().sqr3().modify(|w| {
+                        self.sqr3().modify(|w| {
                             w.set_sq(_i - 9, channel);
                         });
                     }
                     14..=15 => {
-                        T::regs().sqr4().modify(|w| {
+                        self.sqr4().modify(|w| {
                             w.set_sq(_i - 14, channel);
                         });
                     }
@@ -375,20 +372,20 @@ impl<T: Instance> super::SealedAnyInstance for T {
             }
 
             #[cfg(adc_h5)]
-            T::regs().difsel().write(|w| w.set_difsel(difsel));
+            self.difsel().write(|w| w.set_difsel(difsel));
 
             // On G0 and U0 enabled channels are sampled from 0 to last channel.
             // It is possible to add up to 8 sequences if CHSELRMOD = 1.
             // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
             #[cfg(adc_u0)]
-            T::regs().chselr().modify(|reg| {
+            self.chselr().modify(|reg| {
                 reg.set_chsel(channel_mask);
             });
         }
     }
 }
 
-impl<'d, T: Instance> Adc<'d, T> {
+impl<'d, T: Instance<Regs = crate::pac::adc::Adc>> Adc<'d, T> {
     /// Enable the voltage regulator
     fn init_regulator() {
         rcc::enable_and_reset::<T>();