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authorDario Nieuwenhuis <[email protected]>2021-06-07 14:41:22 +0200
committerGitHub <[email protected]>2021-06-07 14:41:22 +0200
commit2b18440becf00a21392f2b20e2e5ee4a0ec7615d (patch)
tree4711a3b8e913653546f06b466c91bb25f7f53274 /embassy-stm32/src/clock.rs
parentf752700df5a20703a3b4d746a524137ef0972b52 (diff)
parenta63388874a15eb6d9358801499e9164f3068a830 (diff)
Merge pull request #230 from lulf/update-regen-peripherals
Update after RCC regen and register fix
Diffstat (limited to 'embassy-stm32/src/clock.rs')
-rw-r--r--embassy-stm32/src/clock.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/clock.rs b/embassy-stm32/src/clock.rs
index 075b80118..7f478e790 100644
--- a/embassy-stm32/src/clock.rs
+++ b/embassy-stm32/src/clock.rs
@@ -83,7 +83,7 @@ impl<T: Instance> Clock<T> {
83 unsafe { 83 unsafe {
84 let rcc = crate::pac::RCC; 84 let rcc = crate::pac::RCC;
85 rcc.apb1enr() 85 rcc.apb1enr()
86 .modify(|w| w.set_tim2en(crate::pac::rcc::vals::Lptimen::ENABLED)); 86 .modify(|w| w.set_tim2en(true));
87 rcc.apb1rstr().modify(|w| w.set_tim2rst(true)); 87 rcc.apb1rstr().modify(|w| w.set_tim2rst(true));
88 rcc.apb1rstr().modify(|w| w.set_tim2rst(false)); 88 rcc.apb1rstr().modify(|w| w.set_tim2rst(false));
89 } 89 }