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authorxoviat <[email protected]>2023-07-22 11:54:54 -0500
committerxoviat <[email protected]>2023-07-22 11:54:54 -0500
commit64f8a779ca4453a40f07433c0bb1ebcaeeeba74c (patch)
tree36b6bf4fdaf4ce8524320743effb894e67c4b8e9 /embassy-stm32/src/dac/mod.rs
parent5693ed1178bf77fc131749b65d27bbaf3b3cf3fd (diff)
stm32: add dac fix
Diffstat (limited to 'embassy-stm32/src/dac/mod.rs')
-rw-r--r--embassy-stm32/src/dac/mod.rs3
1 files changed, 3 insertions, 0 deletions
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 31a2d8863..3d58914b3 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -51,7 +51,10 @@ impl Ch1Trigger {
51 fn tsel(&self) -> dac::vals::Tsel1 { 51 fn tsel(&self) -> dac::vals::Tsel1 {
52 match self { 52 match self {
53 Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO, 53 Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
54 #[cfg(not(dac_v3))]
54 Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO, 55 Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
56 #[cfg(dac_v3)]
57 Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM1_TRGO,
55 Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO, 58 Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
56 Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO, 59 Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
57 Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO, 60 Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO,