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authorJuliDi <[email protected]>2023-06-25 10:53:35 +0200
committerJuliDi <[email protected]>2023-06-25 10:53:35 +0200
commitdf944edeef738590f481d35ee9e2a1afb09601fa (patch)
tree90ecdad19962b14be3999cf22cde0097981fb085 /embassy-stm32/src/dac
parent388d3e273d3d003e6a058b4bad9e2517dd33d626 (diff)
fix minor issues with splitting channels etc
Diffstat (limited to 'embassy-stm32/src/dac')
-rw-r--r--embassy-stm32/src/dac/mod.rs46
1 files changed, 33 insertions, 13 deletions
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index e87292b86..3dcd6b771 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -168,9 +168,9 @@ pub trait DacChannel<T: Instance, Tx> {
168 } 168 }
169} 169}
170 170
171pub struct Dac<'d, T: Instance, Tx> { 171pub struct Dac<'d, T: Instance, TxCh1, TxCh2> {
172 ch1: DacCh1<'d, T, Tx>, 172 ch1: DacCh1<'d, T, TxCh1>,
173 ch2: DacCh2<'d, T, Tx>, 173 ch2: DacCh2<'d, T, TxCh2>,
174} 174}
175 175
176pub struct DacCh1<'d, T: Instance, Tx> { 176pub struct DacCh1<'d, T: Instance, Tx> {
@@ -220,7 +220,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
220 /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled. 220 /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
221 /// 221 ///
222 /// **Important:** Channel 1 has to be configured for the DAC instance! 222 /// **Important:** Channel 1 has to be configured for the DAC instance!
223 async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error> 223 pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
224 where 224 where
225 Tx: Dma<T>, 225 Tx: Dma<T>,
226 { 226 {
@@ -297,11 +297,11 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
297impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> { 297impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
298 /// Perform initialisation steps for the DAC 298 /// Perform initialisation steps for the DAC
299 pub fn new_ch2( 299 pub fn new_ch2(
300 peri: impl Peripheral<P = T> + 'd, 300 _peri: impl Peripheral<P = T> + 'd,
301 dma: impl Peripheral<P = Tx> + 'd, 301 dma: impl Peripheral<P = Tx> + 'd,
302 _pin: impl Peripheral<P = impl DacPin<T, 2>> + 'd, 302 _pin: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
303 ) -> Self { 303 ) -> Self {
304 into_ref!(peri, dma); 304 into_ref!(_peri, dma);
305 T::enable(); 305 T::enable();
306 T::reset(); 306 T::reset();
307 307
@@ -335,7 +335,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
335 /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled. 335 /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
336 /// 336 ///
337 /// **Important:** Channel 1 has to be configured for the DAC instance! 337 /// **Important:** Channel 1 has to be configured for the DAC instance!
338 async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error> 338 pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
339 where 339 where
340 Tx: Dma<T>, 340 Tx: Dma<T>,
341 { 341 {
@@ -409,11 +409,11 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
409 } 409 }
410} 410}
411 411
412impl<'d, T: Instance, Tx> Dac<'d, T, Tx> { 412impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
413 pub fn new( 413 pub fn new(
414 peri: impl Peripheral<P = T> + 'd, 414 peri: impl Peripheral<P = T> + 'd,
415 dma_ch1: impl Peripheral<P = Tx> + 'd, 415 dma_ch1: impl Peripheral<P = TxCh1> + 'd,
416 dma_ch2: impl Peripheral<P = Tx> + 'd, 416 dma_ch2: impl Peripheral<P = TxCh2> + 'd,
417 _pin_ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd, 417 _pin_ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
418 _pin_ch2: impl Peripheral<P = impl DacPin<T, 2>> + 'd, 418 _pin_ch2: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
419 ) -> Self { 419 ) -> Self {
@@ -437,15 +437,35 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
437 dac_ch1.enable_channel().unwrap(); 437 dac_ch1.enable_channel().unwrap();
438 dac_ch1.set_trigger_enable(true).unwrap(); 438 dac_ch1.set_trigger_enable(true).unwrap();
439 439
440 dac_ch1.set_channel_mode(0).unwrap(); 440 dac_ch2.set_channel_mode(0).unwrap();
441 dac_ch1.enable_channel().unwrap(); 441 dac_ch2.enable_channel().unwrap();
442 dac_ch1.set_trigger_enable(true).unwrap(); 442 dac_ch2.set_trigger_enable(true).unwrap();
443 443
444 Self { 444 Self {
445 ch1: dac_ch1, 445 ch1: dac_ch1,
446 ch2: dac_ch2, 446 ch2: dac_ch2,
447 } 447 }
448 } 448 }
449
450 pub fn split(self) -> (DacCh1<'d, T, TxCh1>, DacCh2<'d, T, TxCh2>) {
451 (self.ch1, self.ch2)
452 }
453
454 pub fn ch1_mut(&mut self) -> &mut DacCh1<'d, T, TxCh1> {
455 &mut self.ch1
456 }
457
458 pub fn ch2_mut(&mut self) -> &mut DacCh2<'d, T, TxCh2> {
459 &mut self.ch2
460 }
461
462 pub fn ch1(&mut self) -> &DacCh1<'d, T, TxCh1> {
463 &self.ch1
464 }
465
466 pub fn ch2(&mut self) -> &DacCh2<'d, T, TxCh2> {
467 &self.ch2
468 }
449} 469}
450 470
451impl<'d, T: Instance, Tx> DacChannel<T, Tx> for DacCh1<'d, T, Tx> { 471impl<'d, T: Instance, Tx> DacChannel<T, Tx> for DacCh1<'d, T, Tx> {