diff options
| author | elagil <[email protected]> | 2024-11-28 17:36:14 +0100 |
|---|---|---|
| committer | elagil <[email protected]> | 2024-11-28 17:39:39 +0100 |
| commit | 152d8ee0d9526a9b5d41350385ee2b2102c0c43f (patch) | |
| tree | 6453a2fd6f8946713f6da28ee2665475118cc0ae /embassy-stm32/src/dma | |
| parent | 8954c053fbb0ce83d4bcdec4bf84a26874421696 (diff) | |
fix: make `write_immediate()` for ring buffers right-aligned
Diffstat (limited to 'embassy-stm32/src/dma')
| -rw-r--r-- | embassy-stm32/src/dma/ringbuffer/mod.rs | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/embassy-stm32/src/dma/ringbuffer/mod.rs b/embassy-stm32/src/dma/ringbuffer/mod.rs index 25bdc7522..4dc1b51a9 100644 --- a/embassy-stm32/src/dma/ringbuffer/mod.rs +++ b/embassy-stm32/src/dma/ringbuffer/mod.rs | |||
| @@ -252,9 +252,13 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 252 | } | 252 | } |
| 253 | 253 | ||
| 254 | /// Write elements directly to the buffer. | 254 | /// Write elements directly to the buffer. |
| 255 | /// | ||
| 256 | /// Data is aligned towards the end of the buffer. | ||
| 255 | pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), Error> { | 257 | pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), Error> { |
| 258 | let start = self.cap() - buf.len(); | ||
| 259 | |||
| 256 | for (i, data) in buf.iter().enumerate() { | 260 | for (i, data) in buf.iter().enumerate() { |
| 257 | self.write_buf(i, *data) | 261 | self.write_buf(start + i, *data) |
| 258 | } | 262 | } |
| 259 | let written = buf.len().min(self.cap()); | 263 | let written = buf.len().min(self.cap()); |
| 260 | Ok((written, self.cap() - written)) | 264 | Ok((written, self.cap() - written)) |
