stm32/dma: impl all variants

6 files changed, 553 insertions, 340 deletions

diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
new file mode 100644
index 000000000..9449d4bf8
--- /dev/null
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -0,0 +1,222 @@
+#![macro_use]
+
+use core::future::Future;
+use core::task::Poll;
+
+use atomic_polyfill::{AtomicU8, Ordering};
+use embassy::interrupt::{Interrupt, InterruptExt};
+use embassy::util::{AtomicWaker, OnDrop};
+use futures::future::poll_fn;
+
+use crate::dma::{Channel, Request};
+use crate::interrupt;
+use crate::pac;
+use crate::pac::bdma::vals;
+use crate::rcc::sealed::RccPeripheral;
+
+const CH_COUNT: usize = pac::peripheral_count!(bdma) * 8;
+const CH_STATUS_NONE: u8 = 0;
+const CH_STATUS_COMPLETED: u8 = 1;
+const CH_STATUS_ERROR: u8 = 2;
+
+struct State {
+    ch_wakers: [AtomicWaker; CH_COUNT],
+    ch_status: [AtomicU8; CH_COUNT],
+}
+
+impl State {
+    const fn new() -> Self {
+        const AW: AtomicWaker = AtomicWaker::new();
+        const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
+        Self {
+            ch_wakers: [AW; CH_COUNT],
+            ch_status: [AU; CH_COUNT],
+        }
+    }
+}
+
+static STATE: State = State::new();
+
+#[allow(unused)]
+pub(crate) async unsafe fn do_transfer(
+    dma: pac::bdma::Dma,
+    channel_number: u8,
+    state_number: u8,
+    request: Request,
+    dir: vals::Dir,
+    peri_addr: *const u8,
+    mem_addr: *mut u8,
+    mem_len: usize,
+    #[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
+    #[cfg(dmamux)] dmamux_ch_num: u8,
+) {
+    // ndtr is max 16 bits.
+    assert!(mem_len <= 0xFFFF);
+
+    let ch = dma.ch(channel_number as _);
+
+    // Reset status
+    // Generate a DMB here to flush the store buffer (M7) before enabling the DMA
+    STATE.ch_status[state_number as usize].store(CH_STATUS_NONE, Ordering::Release);
+
+    let on_drop = OnDrop::new(|| unsafe {
+        ch.cr().modify(|w| {
+            w.set_tcie(false);
+            w.set_teie(false);
+            w.set_en(false);
+        });
+        while ch.cr().read().en() {}
+    });
+
+    #[cfg(dmamux)]
+    super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
+
+    #[cfg(bdma_v2)]
+    critical_section::with(|_| {
+        dma.cselr()
+            .modify(|w| w.set_cs(channel_number as _, request))
+    });
+
+    ch.par().write_value(peri_addr as u32);
+    ch.mar().write_value(mem_addr as u32);
+    ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
+    ch.cr().write(|w| {
+        w.set_psize(vals::Size::BITS8);
+        w.set_msize(vals::Size::BITS8);
+        w.set_minc(vals::Inc::ENABLED);
+        w.set_dir(dir);
+        w.set_teie(true);
+        w.set_tcie(true);
+        w.set_en(true);
+    });
+
+    let res = poll_fn(|cx| {
+        STATE.ch_wakers[state_number as usize].register(cx.waker());
+        match STATE.ch_status[state_number as usize].load(Ordering::Acquire) {
+            CH_STATUS_NONE => Poll::Pending,
+            x => Poll::Ready(x),
+        }
+    })
+    .await;
+
+    on_drop.defuse();
+
+    // TODO handle error
+    assert!(res == CH_STATUS_COMPLETED);
+}
+
+macro_rules! dma_num {
+    (DMA1) => {
+        0
+    };
+    (DMA2) => {
+        1
+    };
+    (BDMA) => {
+        0
+    };
+}
+
+unsafe fn on_irq() {
+    pac::peripherals! {
+        (bdma, $dma:ident) => {
+                let isr = pac::$dma.isr().read();
+                pac::$dma.ifcr().write_value(isr);
+                let dman = dma_num!($dma);
+
+                for chn in 0..crate::pac::dma_channels_count!($dma) {
+                    let n = dman * 8 + chn;
+                    if isr.teif(chn) {
+                        STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
+                        STATE.ch_wakers[n].wake();
+                    } else if isr.tcif(chn) {
+                        STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
+                        STATE.ch_wakers[n].wake();
+                    }
+                }
+        };
+    }
+}
+
+
+/// safety: must be called only once
+pub(crate) unsafe fn init() {
+    pac::interrupts! {
+        (DMA, $irq:ident) => {
+            crate::interrupt::$irq::steal().enable();
+        };
+    }
+    pac::peripherals! {
+        (bdma, $peri:ident) => {
+            crate::peripherals::$peri::enable();
+        };
+    }
+}
+
+pac::bdma_channels! {
+    ($channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
+        impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {}
+        impl Channel for crate::peripherals::$channel_peri
+        {
+            type ReadFuture<'a> = impl Future<Output = ()>;
+            type WriteFuture<'a> = impl Future<Output = ()>;
+
+            fn read<'a>(
+                &'a mut self,
+                request: Request,
+                src: *mut u8,
+                buf: &'a mut [u8],
+            ) -> Self::ReadFuture<'a> {
+                unsafe {
+                    do_transfer(
+                        crate::pac::$dma_peri,
+                        $channel_num,
+                        (dma_num!($dma_peri) * 8) + $channel_num,
+                        request,
+                        vals::Dir::FROMPERIPHERAL,
+                        src,
+                        buf.as_mut_ptr(),
+                        buf.len(),
+                        #[cfg(dmamux)]
+                        <Self as super::dmamux::MuxChannel>::DMAMUX_REGS,
+                        #[cfg(dmamux)]
+                        <Self as super::dmamux::MuxChannel>::DMAMUX_CH_NUM,
+                    )
+                }
+            }
+
+            fn write<'a>(
+                &'a mut self,
+                request: Request,
+                buf: &'a [u8],
+                dst: *mut u8,
+            ) -> Self::WriteFuture<'a> {
+                unsafe {
+                    do_transfer(
+                        crate::pac::$dma_peri,
+                        $channel_num,
+                        (dma_num!($dma_peri) * 8) + $channel_num,
+                        request,
+                        vals::Dir::FROMMEMORY,
+                        dst,
+                        buf.as_ptr() as *mut u8,
+                        buf.len(),
+                        #[cfg(dmamux)]
+                        <Self as super::dmamux::MuxChannel>::DMAMUX_REGS,
+                        #[cfg(dmamux)]
+                        <Self as super::dmamux::MuxChannel>::DMAMUX_CH_NUM,
+                    )
+                }
+            }
+        }
+    };
+}
+
+pac::interrupts! {
+    (DMA, $irq:ident) => {
+        #[crate::interrupt]
+        unsafe fn $irq () {
+            on_irq()
+        }
+    };
+}
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
new file mode 100644
index 000000000..b0df6ddc5
--- /dev/null
+++ b/embassy-stm32/src/dma/dma.rs
@@ -0,0 +1,210 @@
+use core::task::Poll;
+
+use atomic_polyfill::{AtomicU8, Ordering};
+use core::future::Future;
+use embassy::interrupt::{Interrupt, InterruptExt};
+use embassy::util::AtomicWaker;
+use futures::future::poll_fn;
+
+use crate::interrupt;
+use crate::pac;
+use crate::pac::dma::{regs, vals};
+use crate::rcc::sealed::RccPeripheral;
+
+use super::{Channel, Request};
+
+const CH_COUNT: usize = pac::peripheral_count!(DMA) * 8;
+const CH_STATUS_NONE: u8 = 0;
+const CH_STATUS_COMPLETED: u8 = 1;
+const CH_STATUS_ERROR: u8 = 2;
+
+struct State {
+    ch_wakers: [AtomicWaker; CH_COUNT],
+    ch_status: [AtomicU8; CH_COUNT],
+}
+
+impl State {
+    const fn new() -> Self {
+        const AW: AtomicWaker = AtomicWaker::new();
+        const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
+        Self {
+            ch_wakers: [AW; CH_COUNT],
+            ch_status: [AU; CH_COUNT],
+        }
+    }
+}
+
+static STATE: State = State::new();
+
+//async unsafe fn do_transfer(ch: &mut impl Channel, ch_func: u8, src: *const u8, dst: &mut [u8]) {
+
+pub(crate) async unsafe fn do_transfer(
+    dma: pac::dma::Dma,
+    channel_number: u8,
+    state_number: u8,
+    request: Request,
+    dir: vals::Dir,
+    peri_addr: *const u8,
+    mem_addr: *mut u8,
+    mem_len: usize,
+    #[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
+    #[cfg(dmamux)] dmamux_ch_num: u8,
+) {
+    // ndtr is max 16 bits.
+    assert!(mem_len <= 0xFFFF);
+
+    // Reset status
+    // Generate a DMB here to flush the store buffer (M7) before enabling the DMA
+    STATE.ch_status[state_number as usize].store(CH_STATUS_NONE, Ordering::Release);
+
+    let ch = dma.st(channel_number as _);
+
+    #[cfg(dmamux)]
+    super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
+
+    unsafe {
+        ch.par().write_value(peri_addr as u32);
+        ch.m0ar().write_value(mem_addr as u32);
+        ch.ndtr().write_value(regs::Ndtr(mem_len as _));
+        ch.cr().write(|w| {
+            w.set_dir(dir);
+            w.set_msize(vals::Size::BITS8);
+            w.set_psize(vals::Size::BITS8);
+            w.set_minc(vals::Inc::INCREMENTED);
+            w.set_pinc(vals::Inc::FIXED);
+            w.set_teie(true);
+            w.set_tcie(true);
+            w.set_en(true);
+
+            #[cfg(dma_v2)]
+            w.set_chsel(request);
+        });
+    }
+
+    let res = poll_fn(|cx| {
+        let n = channel_number as usize;
+        STATE.ch_wakers[n].register(cx.waker());
+        match STATE.ch_status[n].load(Ordering::Acquire) {
+            CH_STATUS_NONE => Poll::Pending,
+            x => Poll::Ready(x),
+        }
+    })
+    .await;
+
+    // TODO handle error
+    assert!(res == CH_STATUS_COMPLETED);
+}
+
+macro_rules! dma_num {
+    (DMA1) => {
+        0
+    };
+    (DMA2) => {
+        1
+    };
+}
+
+unsafe fn on_irq() {
+    pac::peripherals! {
+        (dma, $dma:ident) => {
+            for isrn in 0..2 {
+                let isr = pac::$dma.isr(isrn).read();
+                pac::$dma.ifcr(isrn).write_value(isr);
+                let dman = dma_num!($dma);
+
+                for chn in 0..4 {
+                    let n = dman * 8 + isrn * 4 + chn;
+                    if isr.teif(chn) {
+                        STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
+                        STATE.ch_wakers[n].wake();
+                    } else if isr.tcif(chn) {
+                        STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
+                        STATE.ch_wakers[n].wake();
+                    }
+                }
+            }
+        };
+    }
+}
+
+/// safety: must be called only once
+pub(crate) unsafe fn init() {
+    pac::interrupts! {
+        (DMA, $irq:ident) => {
+            interrupt::$irq::steal().enable();
+        };
+    }
+    pac::peripherals! {
+        (dma, $peri:ident) => {
+            crate::peripherals::$peri::enable();
+        };
+    }
+}
+
+pac::dma_channels! {
+    ($channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
+        impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {}
+        impl Channel for crate::peripherals::$channel_peri
+        {
+            type ReadFuture<'a> = impl Future<Output = ()>;
+            type WriteFuture<'a> = impl Future<Output = ()>;
+
+            fn read<'a>(
+                &'a mut self,
+                request: Request,
+                src: *mut u8,
+                buf: &'a mut [u8],
+            ) -> Self::ReadFuture<'a> {
+                unsafe {
+                    do_transfer(
+                        crate::pac::$dma_peri,
+                        $channel_num,
+                        (dma_num!($dma_peri) * 8) + $channel_num,
+                        request,
+                        vals::Dir::PERIPHERALTOMEMORY,
+                        src,
+                        buf.as_mut_ptr(),
+                        buf.len(),
+                        #[cfg(dmamux)]
+                        <Self as super::dmamux::MuxChannel>::DMAMUX_REGS,
+                        #[cfg(dmamux)]
+                        <Self as super::dmamux::MuxChannel>::DMAMUX_CH_NUM,
+                    )
+                }
+            }
+
+            fn write<'a>(
+                &'a mut self,
+                request: Request,
+                buf: &'a [u8],
+                dst: *mut u8,
+            ) -> Self::WriteFuture<'a> {
+                unsafe {
+                    do_transfer(
+                        crate::pac::$dma_peri,
+                        $channel_num,
+                        (dma_num!($dma_peri) * 8) + $channel_num,
+                        request,
+                        vals::Dir::MEMORYTOPERIPHERAL,
+                        dst,
+                        buf.as_ptr() as *mut u8,
+                        buf.len(),
+                        #[cfg(dmamux)]
+                        <Self as super::dmamux::MuxChannel>::DMAMUX_REGS,
+                        #[cfg(dmamux)]
+                        <Self as super::dmamux::MuxChannel>::DMAMUX_CH_NUM,
+                    )
+                }
+            }
+        }
+    };
+}
+
+pac::interrupts! {
+    (DMA, $irq:ident) => {
+        #[crate::interrupt]
+        unsafe fn $irq () {
+            on_irq()
+        }
+    };
+}
diff --git a/embassy-stm32/src/dma/dmamux.rs b/embassy-stm32/src/dma/dmamux.rs
new file mode 100644
index 000000000..ca2879c2e
--- /dev/null
+++ b/embassy-stm32/src/dma/dmamux.rs
@@ -0,0 +1,61 @@
+#![macro_use]
+
+use crate::pac;
+use crate::peripherals;
+
+pub(crate) unsafe fn configure_dmamux(
+    dmamux_regs: pac::dmamux::Dmamux,
+    dmamux_ch_num: u8,
+    request: u8,
+) {
+    let ch_mux_regs = dmamux_regs.ccr(dmamux_ch_num as _);
+    ch_mux_regs.write(|reg| {
+        reg.set_nbreq(0);
+        reg.set_dmareq_id(request);
+    });
+
+    ch_mux_regs.modify(|reg| {
+        reg.set_ege(true);
+    });
+}
+
+pub(crate) trait MuxChannel {
+    const DMAMUX_CH_NUM: u8;
+    const DMAMUX_REGS: pac::dmamux::Dmamux;
+}
+
+macro_rules! dma_num {
+    (DMA1) => {
+        0
+    };
+    (DMA2) => {
+        1
+    };
+    (BDMA) => {
+        0
+    };
+}
+
+macro_rules! dmamux_peri {
+    (DMA1) => {
+        crate::pac::DMAMUX1
+    };
+    (DMA2) => {
+        crate::pac::DMAMUX1
+    };
+    (BDMA) => {
+        crate::pac::DMAMUX1
+    };
+}
+
+pac::bdma_channels! {
+    ($channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
+        impl MuxChannel for peripherals::$channel_peri {
+            const DMAMUX_CH_NUM: u8 = (dma_num!($dma_peri) * 8) + $channel_num;
+            const DMAMUX_REGS: pac::dmamux::Dmamux = dmamux_peri!($dma_peri);
+        }
+    };
+}
+
+/// safety: must be called only once
+pub(crate) unsafe fn init() {}
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index ed080cd16..ebad3d7b6 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -1,9 +1,62 @@
-#![macro_use]
+#[cfg(bdma)]
+mod bdma;
+#[cfg(dma)]
+mod dma;
+#[cfg(dmamux)]
+mod dmamux;
 
-#[cfg_attr(dma_v1, path = "v1.rs")]
-#[cfg_attr(dma_v2, path = "v2.rs")]
-mod _version;
+use core::future::Future;
+use embassy::util::Unborrow;
 
-#[cfg(dma)]
-#[allow(unused)]
-pub use _version::*;
+#[cfg(any(bdma_v2, dma_v2, dmamux))]
+pub type Request = u8;
+#[cfg(not(any(bdma_v2, dma_v2, dmamux)))]
+pub type Request = ();
+
+pub(crate) mod sealed {
+    pub trait Channel {}
+}
+
+pub trait Channel: sealed::Channel {
+    type ReadFuture<'a>: Future<Output = ()> + 'a
+    where
+        Self: 'a;
+
+    type WriteFuture<'a>: Future<Output = ()> + 'a
+    where
+        Self: 'a;
+
+    fn read<'a>(
+        &'a mut self,
+        request: Request,
+        src: *mut u8,
+        buf: &'a mut [u8],
+    ) -> Self::ReadFuture<'a>;
+
+    fn write<'a>(
+        &'a mut self,
+        request: Request,
+        buf: &'a [u8],
+        dst: *mut u8,
+    ) -> Self::WriteFuture<'a>;
+}
+
+pub struct NoDma;
+
+unsafe impl Unborrow for NoDma {
+    type Target = NoDma;
+
+    unsafe fn unborrow(self) -> Self::Target {
+        self
+    }
+}
+
+// safety: must be called only once at startup
+pub(crate) unsafe fn init() {
+    #[cfg(bdma)]
+    bdma::init();
+    #[cfg(dma)]
+    dma::init();
+    #[cfg(dmamux)]
+    dmamux::init();
+}
diff --git a/embassy-stm32/src/dma/v1.rs b/embassy-stm32/src/dma/v1.rs
deleted file mode 100644
index 4544108e5..000000000
--- a/embassy-stm32/src/dma/v1.rs
+++ /dev/null
@@ -1,2 +0,0 @@
-/// safety: must be called only once
-pub(crate) unsafe fn init() {}
diff --git a/embassy-stm32/src/dma/v2.rs b/embassy-stm32/src/dma/v2.rs
deleted file mode 100644
index df3b922ff..000000000
--- a/embassy-stm32/src/dma/v2.rs
+++ /dev/null
@@ -1,331 +0,0 @@
-use core::task::Poll;
-
-use crate::dma_traits::{ReadDma, WriteDma};
-use atomic_polyfill::{AtomicU8, Ordering};
-use core::future::Future;
-use embassy::interrupt::{Interrupt, InterruptExt};
-use embassy::util::AtomicWaker;
-use futures::future::poll_fn;
-
-use crate::interrupt;
-use crate::pac;
-use crate::pac::dma::{regs, vals};
-
-use crate::pac::dma_channels;
-use crate::pac::interrupts;
-use crate::pac::peripheral_count;
-use crate::pac::peripheral_dma_channels;
-use crate::pac::peripherals;
-use crate::peripherals;
-
-const CH_COUNT: usize = peripheral_count!(DMA) * 8;
-const CH_STATUS_NONE: u8 = 0;
-const CH_STATUS_COMPLETED: u8 = 1;
-const CH_STATUS_ERROR: u8 = 2;
-
-struct State {
-    ch_wakers: [AtomicWaker; CH_COUNT],
-    ch_status: [AtomicU8; CH_COUNT],
-}
-
-impl State {
-    const fn new() -> Self {
-        const AW: AtomicWaker = AtomicWaker::new();
-        const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
-        Self {
-            ch_wakers: [AW; CH_COUNT],
-            ch_status: [AU; CH_COUNT],
-        }
-    }
-}
-
-static STATE: State = State::new();
-
-#[allow(unused)] // Used by usart/v1.rs which may or may not be enabled
-pub(crate) async unsafe fn transfer_p2m(
-    ch: &mut impl Channel,
-    ch_func: u8,
-    src: *const u8,
-    dst: &mut [u8],
-) {
-    let n = ch.num();
-    let c = ch.regs();
-
-    // ndtr is max 16 bits.
-    assert!(dst.len() <= 0xFFFF);
-
-    // Reset status
-    // Generate a DMB here to flush the store buffer (M7) before enabling the DMA
-    STATE.ch_status[n].store(CH_STATUS_NONE, Ordering::Release);
-
-    unsafe {
-        c.par().write_value(src as _);
-        c.m0ar().write_value(dst.as_ptr() as _);
-        c.ndtr().write_value(regs::Ndtr(dst.len() as _));
-        c.cr().write(|w| {
-            w.set_dir(vals::Dir::PERIPHERALTOMEMORY);
-            w.set_msize(vals::Size::BITS8);
-            w.set_psize(vals::Size::BITS8);
-            w.set_minc(vals::Inc::INCREMENTED);
-            w.set_pinc(vals::Inc::FIXED);
-            w.set_chsel(ch_func);
-            w.set_teie(true);
-            w.set_tcie(true);
-            w.set_en(true);
-        });
-    }
-
-    let res = poll_fn(|cx| {
-        STATE.ch_wakers[n].register(cx.waker());
-        match STATE.ch_status[n].load(Ordering::Acquire) {
-            CH_STATUS_NONE => Poll::Pending,
-            x => Poll::Ready(x),
-        }
-    })
-    .await;
-
-    // TODO handle error
-    assert!(res == CH_STATUS_COMPLETED);
-}
-
-#[allow(unused)] // Used by usart/v1.rs which may or may not be enabled
-pub(crate) async unsafe fn transfer_m2p(
-    ch: &mut impl Channel,
-    ch_func: u8,
-    src: &[u8],
-    dst: *mut u8,
-) {
-    let n = ch.num();
-    let c = ch.regs();
-
-    // ndtr is max 16 bits.
-    assert!(src.len() <= 0xFFFF);
-
-    // Reset status
-    // Generate a DMB here to flush the store buffer (M7) before enabling the DMA
-    STATE.ch_status[n].store(CH_STATUS_NONE, Ordering::Release);
-
-    unsafe {
-        c.par().write_value(dst as _);
-        c.m0ar().write_value(src.as_ptr() as _);
-        c.ndtr().write_value(regs::Ndtr(src.len() as _));
-        c.cr().write(|w| {
-            w.set_dir(vals::Dir::MEMORYTOPERIPHERAL);
-            w.set_msize(vals::Size::BITS8);
-            w.set_psize(vals::Size::BITS8);
-            w.set_minc(vals::Inc::INCREMENTED);
-            w.set_pinc(vals::Inc::FIXED);
-            w.set_chsel(ch_func);
-            w.set_teie(true);
-            w.set_tcie(true);
-            w.set_en(true);
-        });
-    }
-
-    let res = poll_fn(|cx| {
-        STATE.ch_wakers[n].register(cx.waker());
-        match STATE.ch_status[n].load(Ordering::Acquire) {
-            CH_STATUS_NONE => {
-                let left = c.ndtr().read().ndt();
-                Poll::Pending
-            }
-            x => Poll::Ready(x),
-        }
-    })
-    .await;
-
-    // TODO handle error
-    assert!(res == CH_STATUS_COMPLETED);
-}
-
-unsafe fn on_irq() {
-    peripherals! {
-        (dma, $dma:ident) => {
-            for isrn in 0..2 {
-                let isr = pac::$dma.isr(isrn).read();
-                pac::$dma.ifcr(isrn).write_value(isr);
-                let dman = <peripherals::$dma as sealed::Dma>::num() as usize;
-
-                for chn in 0..4 {
-                    let n = dman * 8 + isrn * 4 + chn;
-                    if isr.teif(chn) {
-                        STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
-                        STATE.ch_wakers[n].wake();
-                    } else if isr.tcif(chn) {
-                        STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
-                        STATE.ch_wakers[n].wake();
-                    }
-                }
-            }
-        };
-    }
-}
-
-/// safety: must be called only once
-pub(crate) unsafe fn init() {
-    interrupts! {
-        (DMA, $irq:ident) => {
-            interrupt::$irq::steal().enable();
-        };
-    }
-}
-
-pub(crate) mod sealed {
-    use super::*;
-
-    pub trait Dma {
-        fn num() -> u8;
-        fn regs() -> &'static pac::dma::Dma;
-    }
-
-    pub trait Channel {
-        fn dma_regs() -> &'static pac::dma::Dma;
-
-        fn num(&self) -> usize;
-
-        fn ch_num(&self) -> u8;
-
-        fn regs(&self) -> pac::dma::St {
-            Self::dma_regs().st(self.ch_num() as _)
-        }
-    }
-
-    pub trait PeripheralChannel<PERI, OP>: Channel {
-        fn request(&self) -> u8;
-    }
-}
-
-pub trait Dma: sealed::Dma + Sized {}
-pub trait Channel: sealed::Channel + Sized {}
-pub trait PeripheralChannel<PERI, OP>: sealed::PeripheralChannel<PERI, OP> + Sized {}
-
-macro_rules! impl_dma {
-    ($peri:ident, $num:expr) => {
-        impl Dma for peripherals::$peri {}
-        impl sealed::Dma for peripherals::$peri {
-            fn num() -> u8 {
-                $num
-            }
-            fn regs() -> &'static pac::dma::Dma {
-                &pac::$peri
-            }
-        }
-    };
-}
-
-macro_rules! impl_dma_channel {
-    ($channel_peri:ident, $dma_peri:ident, $dma_num:expr, $ch_num:expr) => {
-        impl Channel for peripherals::$channel_peri {}
-        impl sealed::Channel for peripherals::$channel_peri {
-            #[inline]
-            fn dma_regs() -> &'static pac::dma::Dma {
-                &crate::pac::$dma_peri
-            }
-
-            fn num(&self) -> usize {
-                ($dma_num * 8) + $ch_num
-            }
-
-            fn ch_num(&self) -> u8 {
-                $ch_num
-            }
-        }
-
-        impl<T> WriteDma<T> for peripherals::$channel_peri
-        where
-            Self: sealed::PeripheralChannel<T, M2P>,
-            T: 'static,
-        {
-            type WriteDmaFuture<'a> = impl Future<Output = ()>;
-
-            fn transfer<'a>(&'a mut self, buf: &'a [u8], dst: *mut u8) -> Self::WriteDmaFuture<'a>
-            where
-                T: 'a,
-            {
-                let request = sealed::PeripheralChannel::<T, M2P>::request(self);
-                unsafe { transfer_m2p(self, request, buf, dst) }
-            }
-        }
-
-        impl<T> ReadDma<T> for peripherals::$channel_peri
-        where
-            Self: sealed::PeripheralChannel<T, P2M>,
-            T: 'static,
-        {
-            type ReadDmaFuture<'a> = impl Future<Output = ()>;
-
-            fn transfer<'a>(
-                &'a mut self,
-                src: *const u8,
-                buf: &'a mut [u8],
-            ) -> Self::ReadDmaFuture<'a>
-            where
-                T: 'a,
-            {
-                let request = sealed::PeripheralChannel::<T, P2M>::request(self);
-                unsafe { transfer_p2m(self, request, src, buf) }
-            }
-        }
-    };
-}
-
-peripherals! {
-    (dma, DMA1) => {
-        impl_dma!(DMA1, 0);
-        dma_channels! {
-            ($channel_peri:ident, DMA1, $channel_num:expr) => {
-                impl_dma_channel!($channel_peri, DMA1, 0, $channel_num);
-            };
-        }
-    };
-    (dma, DMA2) => {
-        impl_dma!(DMA2, 1);
-        dma_channels! {
-            ($channel_peri:ident, DMA2, $channel_num:expr) => {
-                impl_dma_channel!($channel_peri, DMA2, 1, $channel_num);
-            };
-        }
-    };
-}
-
-interrupts! {
-    (DMA, $irq:ident) => {
-        #[crate::interrupt]
-        unsafe fn $irq () {
-            on_irq()
-        }
-    };
-}
-
-pub struct P2M;
-pub struct M2P;
-
-#[cfg(usart)]
-use crate::usart;
-peripheral_dma_channels! {
-    ($peri:ident, usart, $kind:ident, RX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr, $event_num:expr) => {
-        impl usart::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
-        impl usart::sealed::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
-
-        impl sealed::PeripheralChannel<peripherals::$peri, P2M> for peripherals::$channel_peri {
-            fn request(&self) -> u8 {
-                $event_num
-            }
-        }
-
-        impl PeripheralChannel<peripherals::$peri, P2M> for peripherals::$channel_peri { }
-    };
-
-    ($peri:ident, usart, $kind:ident, TX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr, $event_num:expr) => {
-        impl usart::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
-        impl usart::sealed::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
-
-        impl sealed::PeripheralChannel<peripherals::$peri, M2P> for peripherals::$channel_peri {
-            fn request(&self) -> u8 {
-                $event_num
-            }
-        }
-
-        impl PeripheralChannel<peripherals::$peri, M2P> for peripherals::$channel_peri { }
-    };
-}