diff options
| author | elagil <[email protected]> | 2025-08-25 21:10:59 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2025-09-05 14:43:29 +0200 |
| commit | 3d161e98a1a56d6d73473c40431480d53ee67b70 (patch) | |
| tree | a2066f78262ee922f4f95e488cefc6cff6c768ec /embassy-stm32/src/dma | |
| parent | 7a62b8eee8f2f466fbe1878aab42d63aa171ddaa (diff) | |
fix: simplify
Diffstat (limited to 'embassy-stm32/src/dma')
| -rw-r--r-- | embassy-stm32/src/dma/gpdma/ringbuffered.rs | 23 | ||||
| -rw-r--r-- | embassy-stm32/src/dma/ringbuffer/mod.rs | 55 |
2 files changed, 5 insertions, 73 deletions
diff --git a/embassy-stm32/src/dma/gpdma/ringbuffered.rs b/embassy-stm32/src/dma/gpdma/ringbuffered.rs index 88ec666dc..f9d77ab73 100644 --- a/embassy-stm32/src/dma/gpdma/ringbuffered.rs +++ b/embassy-stm32/src/dma/gpdma/ringbuffered.rs | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | //! GPDMA ring buffer implementation. | 1 | //! GPDMA ring buffer implementation. |
| 2 | //! | 2 | //! |
| 3 | //! FIXME: add request_pause functionality? | 3 | //! FIXME: Add request_pause functionality? |
| 4 | //! FIXME: Stop the DMA, if a user does not queue new transfers (chain of linked-list items ends automatically). | ||
| 4 | use core::future::poll_fn; | 5 | use core::future::poll_fn; |
| 5 | use core::sync::atomic::{fence, Ordering}; | 6 | use core::sync::atomic::{fence, Ordering}; |
| 6 | use core::task::Waker; | 7 | use core::task::Waker; |
| @@ -257,23 +258,9 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> { | |||
| 257 | 258 | ||
| 258 | /// Write an exact number of elements to the ringbuffer. | 259 | /// Write an exact number of elements to the ringbuffer. |
| 259 | pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, Error> { | 260 | pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, Error> { |
| 260 | // return self | 261 | self.ringbuf |
| 261 | // .ringbuf | 262 | .write_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer) |
| 262 | // .write_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer) | 263 | .await |
| 263 | // .await; | ||
| 264 | |||
| 265 | let mut remaining_cap = 0; | ||
| 266 | let mut written_len = 0; | ||
| 267 | |||
| 268 | while written_len < buffer.len() { | ||
| 269 | (written_len, remaining_cap) = self | ||
| 270 | .ringbuf | ||
| 271 | .write_half(&mut DmaCtrlImpl(self.channel.reborrow()), buffer) | ||
| 272 | .await?; | ||
| 273 | // info!("Written: {}/{}", written_len, buffer.len()); | ||
| 274 | } | ||
| 275 | |||
| 276 | Ok(remaining_cap) | ||
| 277 | } | 264 | } |
| 278 | 265 | ||
| 279 | /// Wait for any ring buffer write error. | 266 | /// Wait for any ring buffer write error. |
diff --git a/embassy-stm32/src/dma/ringbuffer/mod.rs b/embassy-stm32/src/dma/ringbuffer/mod.rs index 8d00d822d..2d61204a2 100644 --- a/embassy-stm32/src/dma/ringbuffer/mod.rs +++ b/embassy-stm32/src/dma/ringbuffer/mod.rs | |||
| @@ -216,15 +216,6 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 216 | } | 216 | } |
| 217 | } | 217 | } |
| 218 | 218 | ||
| 219 | /// The buffer half that is in use by the DMA. | ||
| 220 | fn dma_half(&self) -> BufferHalf { | ||
| 221 | if self.read_index.as_index(self.cap(), 0) < self.cap() / 2 { | ||
| 222 | BufferHalf::First | ||
| 223 | } else { | ||
| 224 | BufferHalf::Second | ||
| 225 | } | ||
| 226 | } | ||
| 227 | |||
| 228 | /// Reset the ring buffer to its initial state. The buffer after the reset will be full. | 219 | /// Reset the ring buffer to its initial state. The buffer after the reset will be full. |
| 229 | pub fn reset(&mut self, dma: &mut impl DmaCtrl) { | 220 | pub fn reset(&mut self, dma: &mut impl DmaCtrl) { |
| 230 | dma.reset_complete_count(); | 221 | dma.reset_complete_count(); |
| @@ -325,52 +316,6 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 325 | .await | 316 | .await |
| 326 | } | 317 | } |
| 327 | 318 | ||
| 328 | /// Write the user's current buffer half - not used by the DMA. | ||
| 329 | /// | ||
| 330 | /// Returns a tuple of the written length, and the remaining write capacity in the buffer. | ||
| 331 | #[allow(dead_code)] | ||
| 332 | pub async fn write_half(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<(usize, usize), Error> { | ||
| 333 | let mut written_len = 0; | ||
| 334 | let buffer_len = buffer.len(); | ||
| 335 | |||
| 336 | poll_fn(|cx| { | ||
| 337 | dma.set_waker(cx.waker()); | ||
| 338 | |||
| 339 | let dma_half = self.dma_half(); | ||
| 340 | // let user_half = self.user_half(); | ||
| 341 | |||
| 342 | // if dma_half == user_half { | ||
| 343 | // info!("ups"); | ||
| 344 | // return Poll::Ready(Err(Error::Overrun)); | ||
| 345 | // } | ||
| 346 | |||
| 347 | let write_index = self.write_index.as_index(self.cap(), 0); | ||
| 348 | let target_write_len = match dma_half { | ||
| 349 | BufferHalf::First => self.cap().saturating_sub(write_index), | ||
| 350 | BufferHalf::Second => (self.cap() / 2).saturating_sub(write_index), | ||
| 351 | }; | ||
| 352 | let write_end_index = (target_write_len + written_len).min(buffer_len); | ||
| 353 | |||
| 354 | // info!( | ||
| 355 | // "buf_len: {}, write_len: {}, write_index: {}", | ||
| 356 | // buffer_len, target_write_len, write_index | ||
| 357 | // ); | ||
| 358 | |||
| 359 | match self.write(dma, &buffer[written_len..write_end_index]) { | ||
| 360 | Ok((len, remaining)) => { | ||
| 361 | written_len += len; | ||
| 362 | if written_len == write_end_index { | ||
| 363 | Poll::Ready(Ok((written_len, remaining))) | ||
| 364 | } else { | ||
| 365 | Poll::Pending | ||
| 366 | } | ||
| 367 | } | ||
| 368 | Err(e) => Poll::Ready(Err(e)), | ||
| 369 | } | ||
| 370 | }) | ||
| 371 | .await | ||
| 372 | } | ||
| 373 | |||
| 374 | fn write_raw(&mut self, dma: &mut impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), Error> { | 319 | fn write_raw(&mut self, dma: &mut impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), Error> { |
| 375 | let writable = self.len(dma)?.min(buf.len()); | 320 | let writable = self.len(dma)?.min(buf.len()); |
| 376 | for i in 0..writable { | 321 | for i in 0..writable { |
