diff options
| author | elagil <[email protected]> | 2024-11-17 23:09:51 +0100 |
|---|---|---|
| committer | elagil <[email protected]> | 2024-11-17 23:10:11 +0100 |
| commit | 7ae28163414d0042c4e06cc02de900e67b62df01 (patch) | |
| tree | 4cbc9fbdf85cfcdc5f812fb208a650a366a7874f /embassy-stm32/src/dma | |
| parent | f99d733b616e748eb9c7122b77d6521297d53171 (diff) | |
feat: SAI/ringbuffer add function to wait for any write error
Diffstat (limited to 'embassy-stm32/src/dma')
| -rw-r--r-- | embassy-stm32/src/dma/dma_bdma.rs | 7 | ||||
| -rw-r--r-- | embassy-stm32/src/dma/ringbuffer/mod.rs | 13 |
2 files changed, 20 insertions, 0 deletions
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs index 08c7a5508..90160ed50 100644 --- a/embassy-stm32/src/dma/dma_bdma.rs +++ b/embassy-stm32/src/dma/dma_bdma.rs | |||
| @@ -1006,6 +1006,13 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> { | |||
| 1006 | .await | 1006 | .await |
| 1007 | } | 1007 | } |
| 1008 | 1008 | ||
| 1009 | /// Wait for any ring buffer write error. | ||
| 1010 | pub async fn write_error(&mut self) -> Result<usize, Error> { | ||
| 1011 | self.ringbuf | ||
| 1012 | .write_error(&mut DmaCtrlImpl(self.channel.reborrow())) | ||
| 1013 | .await | ||
| 1014 | } | ||
| 1015 | |||
| 1009 | /// The current length of the ringbuffer | 1016 | /// The current length of the ringbuffer |
| 1010 | pub fn len(&mut self) -> Result<usize, Error> { | 1017 | pub fn len(&mut self) -> Result<usize, Error> { |
| 1011 | Ok(self.ringbuf.len(&mut DmaCtrlImpl(self.channel.reborrow()))?) | 1018 | Ok(self.ringbuf.len(&mut DmaCtrlImpl(self.channel.reborrow()))?) |
diff --git a/embassy-stm32/src/dma/ringbuffer/mod.rs b/embassy-stm32/src/dma/ringbuffer/mod.rs index 0da8c374f..b7f98fbce 100644 --- a/embassy-stm32/src/dma/ringbuffer/mod.rs +++ b/embassy-stm32/src/dma/ringbuffer/mod.rs | |||
| @@ -260,6 +260,19 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 260 | Ok((written, self.cap() - written)) | 260 | Ok((written, self.cap() - written)) |
| 261 | } | 261 | } |
| 262 | 262 | ||
| 263 | /// Wait for any ring buffer write error. | ||
| 264 | pub async fn write_error(&mut self, dma: &mut impl DmaCtrl) -> Result<usize, Error> { | ||
| 265 | poll_fn(|cx| { | ||
| 266 | dma.set_waker(cx.waker()); | ||
| 267 | |||
| 268 | match self.len(dma) { | ||
| 269 | Ok(_) => Poll::Pending, | ||
| 270 | Err(e) => Poll::Ready(Err(e)), | ||
| 271 | } | ||
| 272 | }) | ||
| 273 | .await | ||
| 274 | } | ||
| 275 | |||
| 263 | /// Write an exact number of elements to the ringbuffer. | 276 | /// Write an exact number of elements to the ringbuffer. |
| 264 | pub async fn write_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<usize, Error> { | 277 | pub async fn write_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<usize, Error> { |
| 265 | let mut written_data = 0; | 278 | let mut written_data = 0; |
