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authorLiu Hancheng <[email protected]>2025-01-04 20:16:34 +0800
committerLiu Hancheng <[email protected]>2025-01-04 20:16:34 +0800
commitff526e1604f4e9edc682f4bc270ddc815a860e48 (patch)
treecc6c4e901d9c187d72dee59167a7189fed56ed65 /embassy-stm32/src/dma
parent90b41644261440a535c35c1c75c22ce2606c5037 (diff)
refactor: update DMA transfer functions to use separate memory and peripheral sizes
Diffstat (limited to 'embassy-stm32/src/dma')
-rw-r--r--embassy-stm32/src/dma/dma_bdma.rs38
1 files changed, 26 insertions, 12 deletions
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 1945c3587..8b4b454c0 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -340,7 +340,8 @@ impl AnyChannel {
340 mem_addr: *mut u32, 340 mem_addr: *mut u32,
341 mem_len: usize, 341 mem_len: usize,
342 incr_mem: bool, 342 incr_mem: bool,
343 data_size: WordSize, 343 mem_size: WordSize,
344 peripheral_size: WordSize,
344 options: TransferOptions, 345 options: TransferOptions,
345 ) { 346 ) {
346 let info = self.info(); 347 let info = self.info();
@@ -380,8 +381,8 @@ impl AnyChannel {
380 }); 381 });
381 ch.cr().write(|w| { 382 ch.cr().write(|w| {
382 w.set_dir(dir.into()); 383 w.set_dir(dir.into());
383 w.set_msize(data_size.into()); 384 w.set_msize(mem_size.into());
384 w.set_psize(data_size.into()); 385 w.set_psize(peripheral_size.into());
385 w.set_pl(options.priority.into()); 386 w.set_pl(options.priority.into());
386 w.set_minc(incr_mem); 387 w.set_minc(incr_mem);
387 w.set_pinc(false); 388 w.set_pinc(false);
@@ -414,8 +415,8 @@ impl AnyChannel {
414 ch.mar().write_value(mem_addr as u32); 415 ch.mar().write_value(mem_addr as u32);
415 ch.ndtr().write(|w| w.set_ndt(mem_len as u16)); 416 ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
416 ch.cr().write(|w| { 417 ch.cr().write(|w| {
417 w.set_psize(data_size.into()); 418 w.set_psize(peripheral_size.into());
418 w.set_msize(data_size.into()); 419 w.set_msize(mem_size.into());
419 w.set_minc(incr_mem); 420 w.set_minc(incr_mem);
420 w.set_dir(dir.into()); 421 w.set_dir(dir.into());
421 w.set_teie(true); 422 w.set_teie(true);
@@ -602,27 +603,28 @@ impl<'a> Transfer<'a> {
602 buf.len(), 603 buf.len(),
603 true, 604 true,
604 W::size(), 605 W::size(),
606 W::size(),
605 options, 607 options,
606 ) 608 )
607 } 609 }
608 610
609 /// Create a new write DMA transfer (memory to peripheral). 611 /// Create a new write DMA transfer (memory to peripheral).
610 pub unsafe fn new_write<W: Word>( 612 pub unsafe fn new_write<MW: Word, PW: Word>(
611 channel: impl Peripheral<P = impl Channel> + 'a, 613 channel: impl Peripheral<P = impl Channel> + 'a,
612 request: Request, 614 request: Request,
613 buf: &'a [W], 615 buf: &'a [MW],
614 peri_addr: *mut W, 616 peri_addr: *mut PW,
615 options: TransferOptions, 617 options: TransferOptions,
616 ) -> Self { 618 ) -> Self {
617 Self::new_write_raw(channel, request, buf, peri_addr, options) 619 Self::new_write_raw(channel, request, buf, peri_addr, options)
618 } 620 }
619 621
620 /// Create a new write DMA transfer (memory to peripheral), using raw pointers. 622 /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
621 pub unsafe fn new_write_raw<W: Word>( 623 pub unsafe fn new_write_raw<W: Word, PW: Word>(
622 channel: impl Peripheral<P = impl Channel> + 'a, 624 channel: impl Peripheral<P = impl Channel> + 'a,
623 request: Request, 625 request: Request,
624 buf: *const [W], 626 buf: *const [W],
625 peri_addr: *mut W, 627 peri_addr: *mut PW,
626 options: TransferOptions, 628 options: TransferOptions,
627 ) -> Self { 629 ) -> Self {
628 into_ref!(channel); 630 into_ref!(channel);
@@ -636,6 +638,7 @@ impl<'a> Transfer<'a> {
636 buf.len(), 638 buf.len(),
637 true, 639 true,
638 W::size(), 640 W::size(),
641 W::size(),
639 options, 642 options,
640 ) 643 )
641 } 644 }
@@ -660,6 +663,7 @@ impl<'a> Transfer<'a> {
660 count, 663 count,
661 false, 664 false,
662 W::size(), 665 W::size(),
666 W::size(),
663 options, 667 options,
664 ) 668 )
665 } 669 }
@@ -673,15 +677,23 @@ impl<'a> Transfer<'a> {
673 mem_len: usize, 677 mem_len: usize,
674 incr_mem: bool, 678 incr_mem: bool,
675 data_size: WordSize, 679 data_size: WordSize,
680 peripheral_size: WordSize,
676 options: TransferOptions, 681 options: TransferOptions,
677 ) -> Self { 682 ) -> Self {
678 assert!(mem_len > 0 && mem_len <= 0xFFFF); 683 assert!(mem_len > 0 && mem_len <= 0xFFFF);
679 684
680 channel.configure( 685 channel.configure(
681 _request, dir, peri_addr, mem_addr, mem_len, incr_mem, data_size, options, 686 _request,
687 dir,
688 peri_addr,
689 mem_addr,
690 mem_len,
691 incr_mem,
692 data_size,
693 peripheral_size,
694 options,
682 ); 695 );
683 channel.start(); 696 channel.start();
684
685 Self { channel } 697 Self { channel }
686 } 698 }
687 699
@@ -814,6 +826,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
814 len, 826 len,
815 true, 827 true,
816 data_size, 828 data_size,
829 data_size,
817 options, 830 options,
818 ); 831 );
819 832
@@ -966,6 +979,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
966 len, 979 len,
967 true, 980 true,
968 data_size, 981 data_size,
982 data_size,
969 options, 983 options,
970 ); 984 );
971 985