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authoreverdrone <[email protected]>2025-09-21 14:52:11 +0200
committereverdrone <[email protected]>2025-09-21 14:52:11 +0200
commit500ffc0acb4014e334d9d1f23a45a1f65c02aa17 (patch)
tree78dc077fbd0e39583a848dddd7f706f21b509325 /embassy-stm32/src/exti.rs
parente6e42001a65e2c77cdb6995b7f689fbb4d10d045 (diff)
Fix EXTI, DTS and FLASH for N6 family
Diffstat (limited to 'embassy-stm32/src/exti.rs')
-rw-r--r--embassy-stm32/src/exti.rs16
1 files changed, 8 insertions, 8 deletions
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 9fce78f95..376fdccb8 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -31,11 +31,11 @@ fn cpu_regs() -> pac::exti::Exti {
31 EXTI 31 EXTI
32} 32}
33 33
34#[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50)))] 34#[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50, exti_n6)))]
35fn exticr_regs() -> pac::syscfg::Syscfg { 35fn exticr_regs() -> pac::syscfg::Syscfg {
36 pac::SYSCFG 36 pac::SYSCFG
37} 37}
38#[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))] 38#[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
39fn exticr_regs() -> pac::exti::Exti { 39fn exticr_regs() -> pac::exti::Exti {
40 EXTI 40 EXTI
41} 41}
@@ -45,9 +45,9 @@ fn exticr_regs() -> pac::afio::Afio {
45} 45}
46 46
47unsafe fn on_irq() { 47unsafe fn on_irq() {
48 #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))] 48 #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
49 let bits = EXTI.pr(0).read().0; 49 let bits = EXTI.pr(0).read().0;
50 #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))] 50 #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
51 let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0; 51 let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
52 52
53 // We don't handle or change any EXTI lines above 16. 53 // We don't handle or change any EXTI lines above 16.
@@ -62,9 +62,9 @@ unsafe fn on_irq() {
62 } 62 }
63 63
64 // Clear pending 64 // Clear pending
65 #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))] 65 #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
66 EXTI.pr(0).write_value(Lines(bits)); 66 EXTI.pr(0).write_value(Lines(bits));
67 #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))] 67 #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
68 { 68 {
69 EXTI.rpr(0).write_value(Lines(bits)); 69 EXTI.rpr(0).write_value(Lines(bits));
70 EXTI.fpr(0).write_value(Lines(bits)); 70 EXTI.fpr(0).write_value(Lines(bits));
@@ -239,9 +239,9 @@ impl<'a> ExtiInputFuture<'a> {
239 EXTI.ftsr(0).modify(|w| w.set_line(pin, falling)); 239 EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
240 240
241 // clear pending bit 241 // clear pending bit
242 #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))] 242 #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
243 EXTI.pr(0).write(|w| w.set_line(pin, true)); 243 EXTI.pr(0).write(|w| w.set_line(pin, true));
244 #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))] 244 #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
245 { 245 {
246 EXTI.rpr(0).write(|w| w.set_line(pin, true)); 246 EXTI.rpr(0).write(|w| w.set_line(pin, true));
247 EXTI.fpr(0).write(|w| w.set_line(pin, true)); 247 EXTI.fpr(0).write(|w| w.set_line(pin, true));