diff options
| author | Caleb Garrett <[email protected]> | 2024-02-06 18:37:48 -0500 |
|---|---|---|
| committer | Caleb Garrett <[email protected]> | 2024-02-06 18:37:48 -0500 |
| commit | bfa67c29932ba9b326da0c661b1b03dcee2ef3fe (patch) | |
| tree | fb82ca76f8b3707be3add129028aaafe94b88e18 /embassy-stm32/src/hash | |
| parent | b7db75adff16eb0a4670e926dc664549433654fd (diff) | |
Fix digest interrupt enable.
Diffstat (limited to 'embassy-stm32/src/hash')
| -rw-r--r-- | embassy-stm32/src/hash/v1.rs | 2 | ||||
| -rw-r--r-- | embassy-stm32/src/hash/v2v3.rs | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/embassy-stm32/src/hash/v1.rs b/embassy-stm32/src/hash/v1.rs index 50f9adc83..36beb7c3e 100644 --- a/embassy-stm32/src/hash/v1.rs +++ b/embassy-stm32/src/hash/v1.rs | |||
| @@ -215,7 +215,7 @@ impl<'d, T: Instance> Hash<'d, T> { | |||
| 215 | } | 215 | } |
| 216 | // Register waker, then enable interrupts. | 216 | // Register waker, then enable interrupts. |
| 217 | HASH_WAKER.register(cx.waker()); | 217 | HASH_WAKER.register(cx.waker()); |
| 218 | T::regs().imr().modify(|reg| reg.set_dinie(true)); | 218 | T::regs().imr().modify(|reg| reg.set_dcie(true)); |
| 219 | // Check for completion. | 219 | // Check for completion. |
| 220 | let bits = T::regs().sr().read(); | 220 | let bits = T::regs().sr().read(); |
| 221 | if bits.dcis() { | 221 | if bits.dcis() { |
diff --git a/embassy-stm32/src/hash/v2v3.rs b/embassy-stm32/src/hash/v2v3.rs index 058864568..ba1e05f0c 100644 --- a/embassy-stm32/src/hash/v2v3.rs +++ b/embassy-stm32/src/hash/v2v3.rs | |||
| @@ -244,7 +244,7 @@ impl<'d, T: Instance, D: Dma<T>> Hash<'d, T, D> { | |||
| 244 | } | 244 | } |
| 245 | // Register waker, then enable interrupts. | 245 | // Register waker, then enable interrupts. |
| 246 | HASH_WAKER.register(cx.waker()); | 246 | HASH_WAKER.register(cx.waker()); |
| 247 | T::regs().imr().modify(|reg| reg.set_dinie(true)); | 247 | T::regs().imr().modify(|reg| reg.set_dcie(true)); |
| 248 | // Check for completion. | 248 | // Check for completion. |
| 249 | let bits = T::regs().sr().read(); | 249 | let bits = T::regs().sr().read(); |
| 250 | if bits.dcis() { | 250 | if bits.dcis() { |