stm32: autogenerate clocks struct, enable mux for all chips.

2 files changed, 11 insertions, 9 deletions

diff --git a/embassy-stm32/src/hrtim/mod.rs b/embassy-stm32/src/hrtim/mod.rs
index faefaabbc..3ec646fc3 100644
--- a/embassy-stm32/src/hrtim/mod.rs
+++ b/embassy-stm32/src/hrtim/mod.rs
@@ -10,8 +10,6 @@ pub use traits::Instance;
 #[allow(unused_imports)]
 use crate::gpio::sealed::{AFType, Pin};
 use crate::gpio::AnyPin;
-#[cfg(stm32f334)]
-use crate::rcc::get_freqs;
 use crate::time::Hertz;
 use crate::Peripheral;
 
@@ -182,7 +180,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> {
         T::enable_and_reset();
 
         #[cfg(stm32f334)]
-        if unsafe { get_freqs() }.hrtim.is_some() {
+        if crate::pac::RCC.cfgr3().read().hrtim1sw() == crate::pac::rcc::vals::Timsw::PLL1_P {
             // Enable and and stabilize the DLL
             T::regs().dllcr().modify(|w| {
                 w.set_cal(true);
diff --git a/embassy-stm32/src/hrtim/traits.rs b/embassy-stm32/src/hrtim/traits.rs
index cfd31c47c..dcc2b9ef4 100644
--- a/embassy-stm32/src/hrtim/traits.rs
+++ b/embassy-stm32/src/hrtim/traits.rs
@@ -80,10 +80,12 @@ pub(crate) mod sealed {
 
         fn set_master_frequency(frequency: Hertz) {
             let f = frequency.0;
-            #[cfg(not(stm32f334))]
+
+            // TODO: wire up HRTIM to the RCC mux infra.
+            //#[cfg(stm32f334)]
+            //let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
+            //#[cfg(not(stm32f334))]
             let timer_f = Self::frequency().0;
-            #[cfg(stm32f334)]
-            let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
 
             let psc_min = (timer_f / f) / (u16::MAX as u32 / 32);
             let psc = if Self::regs().isr().read().dllrdy() {
@@ -103,10 +105,12 @@ pub(crate) mod sealed {
 
         fn set_channel_frequency(channel: usize, frequency: Hertz) {
             let f = frequency.0;
-            #[cfg(not(stm32f334))]
+
+            // TODO: wire up HRTIM to the RCC mux infra.
+            //#[cfg(stm32f334)]
+            //let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
+            //#[cfg(not(stm32f334))]
             let timer_f = Self::frequency().0;
-            #[cfg(stm32f334)]
-            let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
 
             let psc_min = (timer_f / f) / (u16::MAX as u32 / 32);
             let psc = if Self::regs().isr().read().dllrdy() {