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| author | Pietro Lorefice <[email protected]> | 2025-06-20 10:47:37 +0200 |
|---|---|---|
| committer | Pietro Lorefice <[email protected]> | 2025-06-20 10:47:37 +0200 |
| commit | 59228e2ab4d70eee356400b2470190885527bbc1 (patch) | |
| tree | 22d24453fba619fee6f5b772448907076a6da380 /embassy-stm32/src/hsem | |
| parent | be5b62bdd469dc7fd68ddb4040b4c0547e65bda8 (diff) | |
stm32: hsem: fix broken CPUID detection
Diffstat (limited to 'embassy-stm32/src/hsem')
| -rw-r--r-- | embassy-stm32/src/hsem/mod.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs index f648bf861..573a1851d 100644 --- a/embassy-stm32/src/hsem/mod.rs +++ b/embassy-stm32/src/hsem/mod.rs | |||
| @@ -46,7 +46,7 @@ pub enum CoreId { | |||
| 46 | #[inline(always)] | 46 | #[inline(always)] |
| 47 | pub fn get_current_coreid() -> CoreId { | 47 | pub fn get_current_coreid() -> CoreId { |
| 48 | let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() }; | 48 | let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() }; |
| 49 | match cpuid & 0x000000F0 { | 49 | match (cpuid & 0x000000F0) >> 4 { |
| 50 | #[cfg(any(stm32wb, stm32wl))] | 50 | #[cfg(any(stm32wb, stm32wl))] |
| 51 | 0x0 => CoreId::Core1, | 51 | 0x0 => CoreId::Core1, |
| 52 | 52 | ||