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authorSüha Ünüvar <[email protected]>2025-08-08 23:01:11 +0800
committerSüha Ünüvar <[email protected]>2025-08-08 23:01:11 +0800
commit5e3221bcc47bc1ce30eaf8d347377d652dbba7e2 (patch)
treee8dfbba23ab4f03efe8df3f0ab1f8d1880fc0749 /embassy-stm32/src/i2c/mod.rs
parentf9da2888c4d0e1a27cbd0f2a915fecb26eb4cc62 (diff)
i2c
Diffstat (limited to 'embassy-stm32/src/i2c/mod.rs')
-rw-r--r--embassy-stm32/src/i2c/mod.rs11
1 files changed, 3 insertions, 8 deletions
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index 825dd240c..5fb49f943 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -158,7 +158,6 @@ impl<'d> I2c<'d, Async, Master> {
158 + 'd, 158 + 'd,
159 tx_dma: Peri<'d, impl TxDma<T>>, 159 tx_dma: Peri<'d, impl TxDma<T>>,
160 rx_dma: Peri<'d, impl RxDma<T>>, 160 rx_dma: Peri<'d, impl RxDma<T>>,
161 freq: Hertz,
162 config: Config, 161 config: Config,
163 ) -> Self { 162 ) -> Self {
164 Self::new_inner( 163 Self::new_inner(
@@ -167,7 +166,6 @@ impl<'d> I2c<'d, Async, Master> {
167 new_pin!(sda, config.sda_af()), 166 new_pin!(sda, config.sda_af()),
168 new_dma!(tx_dma), 167 new_dma!(tx_dma),
169 new_dma!(rx_dma), 168 new_dma!(rx_dma),
170 freq,
171 config, 169 config,
172 ) 170 )
173 } 171 }
@@ -179,7 +177,6 @@ impl<'d> I2c<'d, Blocking, Master> {
179 peri: Peri<'d, T>, 177 peri: Peri<'d, T>,
180 scl: Peri<'d, impl SclPin<T>>, 178 scl: Peri<'d, impl SclPin<T>>,
181 sda: Peri<'d, impl SdaPin<T>>, 179 sda: Peri<'d, impl SdaPin<T>>,
182 freq: Hertz,
183 config: Config, 180 config: Config,
184 ) -> Self { 181 ) -> Self {
185 Self::new_inner( 182 Self::new_inner(
@@ -188,7 +185,6 @@ impl<'d> I2c<'d, Blocking, Master> {
188 new_pin!(sda, config.sda_af()), 185 new_pin!(sda, config.sda_af()),
189 None, 186 None,
190 None, 187 None,
191 freq,
192 config, 188 config,
193 ) 189 )
194 } 190 }
@@ -202,7 +198,6 @@ impl<'d, M: Mode> I2c<'d, M, Master> {
202 sda: Option<Peri<'d, AnyPin>>, 198 sda: Option<Peri<'d, AnyPin>>,
203 tx_dma: Option<ChannelAndRequest<'d>>, 199 tx_dma: Option<ChannelAndRequest<'d>>,
204 rx_dma: Option<ChannelAndRequest<'d>>, 200 rx_dma: Option<ChannelAndRequest<'d>>,
205 freq: Hertz,
206 config: Config, 201 config: Config,
207 ) -> Self { 202 ) -> Self {
208 unsafe { T::EventInterrupt::enable() }; 203 unsafe { T::EventInterrupt::enable() };
@@ -224,14 +219,14 @@ impl<'d, M: Mode> I2c<'d, M, Master> {
224 sda, 219 sda,
225 }, 220 },
226 }; 221 };
227 this.enable_and_init(freq, config); 222 this.enable_and_init(config);
228 223
229 this 224 this
230 } 225 }
231 226
232 fn enable_and_init(&mut self, freq: Hertz, config: Config) { 227 fn enable_and_init(&mut self, config: Config) {
233 self.info.rcc.enable_and_reset(); 228 self.info.rcc.enable_and_reset();
234 self.init(freq, config); 229 self.init(config);
235 } 230 }
236} 231}
237 232