diff options
| author | xoviat <[email protected]> | 2025-12-08 08:19:24 -0600 |
|---|---|---|
| committer | xoviat <[email protected]> | 2025-12-08 08:19:24 -0600 |
| commit | c93da8fc6d76cd6978c0cfbfb3ab42b0285af8d8 (patch) | |
| tree | e745116af2890bdd54821eeb44aed44a3cffff3b /embassy-stm32/src/i2c/v2.rs | |
| parent | 2a738c147111569e4f0968020eec6fb5d5d4e754 (diff) | |
low-power: use scoped block stop
Co-authored-by: hjeldin <[email protected]>
Diffstat (limited to 'embassy-stm32/src/i2c/v2.rs')
| -rw-r--r-- | embassy-stm32/src/i2c/v2.rs | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs index 7ad9978b1..32ce83d40 100644 --- a/embassy-stm32/src/i2c/v2.rs +++ b/embassy-stm32/src/i2c/v2.rs | |||
| @@ -1075,6 +1075,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> { | |||
| 1075 | 1075 | ||
| 1076 | /// Write. | 1076 | /// Write. |
| 1077 | pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> { | 1077 | pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> { |
| 1078 | let _scoped_block_stop = self.info.rcc.block_stop(); | ||
| 1078 | let timeout = self.timeout(); | 1079 | let timeout = self.timeout(); |
| 1079 | if write.is_empty() { | 1080 | if write.is_empty() { |
| 1080 | self.write_internal(address.into(), write, true, timeout) | 1081 | self.write_internal(address.into(), write, true, timeout) |
| @@ -1089,6 +1090,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> { | |||
| 1089 | /// | 1090 | /// |
| 1090 | /// The buffers are concatenated in a single write transaction. | 1091 | /// The buffers are concatenated in a single write transaction. |
| 1091 | pub async fn write_vectored(&mut self, address: Address, write: &[&[u8]]) -> Result<(), Error> { | 1092 | pub async fn write_vectored(&mut self, address: Address, write: &[&[u8]]) -> Result<(), Error> { |
| 1093 | let _scoped_block_stop = self.info.rcc.block_stop(); | ||
| 1092 | let timeout = self.timeout(); | 1094 | let timeout = self.timeout(); |
| 1093 | 1095 | ||
| 1094 | if write.is_empty() { | 1096 | if write.is_empty() { |
| @@ -1120,6 +1122,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> { | |||
| 1120 | 1122 | ||
| 1121 | /// Read. | 1123 | /// Read. |
| 1122 | pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> { | 1124 | pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> { |
| 1125 | let _scoped_block_stop = self.info.rcc.block_stop(); | ||
| 1123 | let timeout = self.timeout(); | 1126 | let timeout = self.timeout(); |
| 1124 | 1127 | ||
| 1125 | if buffer.is_empty() { | 1128 | if buffer.is_empty() { |
| @@ -1132,6 +1135,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> { | |||
| 1132 | 1135 | ||
| 1133 | /// Write, restart, read. | 1136 | /// Write, restart, read. |
| 1134 | pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> { | 1137 | pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> { |
| 1138 | let _scoped_block_stop = self.info.rcc.block_stop(); | ||
| 1135 | let timeout = self.timeout(); | 1139 | let timeout = self.timeout(); |
| 1136 | 1140 | ||
| 1137 | if write.is_empty() { | 1141 | if write.is_empty() { |
| @@ -1157,6 +1161,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> { | |||
| 1157 | /// | 1161 | /// |
| 1158 | /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction | 1162 | /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction |
| 1159 | pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> { | 1163 | pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> { |
| 1164 | let _scoped_block_stop = self.info.rcc.block_stop(); | ||
| 1160 | if operations.is_empty() { | 1165 | if operations.is_empty() { |
| 1161 | return Err(Error::ZeroLengthTransfer); | 1166 | return Err(Error::ZeroLengthTransfer); |
| 1162 | } | 1167 | } |
| @@ -1677,6 +1682,7 @@ impl<'d, M: Mode> I2c<'d, M, MultiMaster> { | |||
| 1677 | /// | 1682 | /// |
| 1678 | /// The listen method is an asynchronous method but it does not require DMA to be asynchronous. | 1683 | /// The listen method is an asynchronous method but it does not require DMA to be asynchronous. |
| 1679 | pub async fn listen(&mut self) -> Result<SlaveCommand, Error> { | 1684 | pub async fn listen(&mut self) -> Result<SlaveCommand, Error> { |
| 1685 | let _scoped_block_stop = self.info.rcc.block_stop(); | ||
| 1680 | let state = self.state; | 1686 | let state = self.state; |
| 1681 | self.info.regs.cr1().modify(|reg| { | 1687 | self.info.regs.cr1().modify(|reg| { |
| 1682 | reg.set_addrie(true); | 1688 | reg.set_addrie(true); |
| @@ -1733,12 +1739,14 @@ impl<'d> I2c<'d, Async, MultiMaster> { | |||
| 1733 | /// | 1739 | /// |
| 1734 | /// Returns the total number of bytes received. | 1740 | /// Returns the total number of bytes received. |
| 1735 | pub async fn respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { | 1741 | pub async fn respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { |
| 1742 | let _scoped_block_stop = self.info.rcc.block_stop(); | ||
| 1736 | let timeout = self.timeout(); | 1743 | let timeout = self.timeout(); |
| 1737 | timeout.with(self.read_dma_internal_slave(buffer, timeout)).await | 1744 | timeout.with(self.read_dma_internal_slave(buffer, timeout)).await |
| 1738 | } | 1745 | } |
| 1739 | 1746 | ||
| 1740 | /// Respond to a read request from an I2C master. | 1747 | /// Respond to a read request from an I2C master. |
| 1741 | pub async fn respond_to_read(&mut self, write: &[u8]) -> Result<SendStatus, Error> { | 1748 | pub async fn respond_to_read(&mut self, write: &[u8]) -> Result<SendStatus, Error> { |
| 1749 | let _scoped_block_stop = self.info.rcc.block_stop(); | ||
| 1742 | let timeout = self.timeout(); | 1750 | let timeout = self.timeout(); |
| 1743 | timeout.with(self.write_dma_internal_slave(write, timeout)).await | 1751 | timeout.with(self.write_dma_internal_slave(write, timeout)).await |
| 1744 | } | 1752 | } |
